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Change subject: smmstorev2: Load the communication buffer at SMM setup
......................................................................
Patch Set 7: Code-Review+2
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Change subject: mb/ocp/*: Remove unused ACPI opregion
......................................................................
Patch Set 3: Code-Review+2
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Change subject: smmstorev2: Load the communication buffer at SMM setup
......................................................................
smmstorev2: Load the communication buffer at SMM setup
This removes the runtime SMI call to set up the communication buffer
for SMMSTORE in favor of setting this buffer up during the installation
of the smihandler.
The reason is that it's less code in the handler and a time costly SMI
is also avoided in ramstage.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b
---
M Documentation/drivers/smmstorev2.md
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/drivers/smmstore/ramstage.c
M src/drivers/smmstore/smi.c
M src/drivers/smmstore/store.c
M src/include/cpu/x86/smm.h
M src/include/smmstore.h
8 files changed, 48 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/79738/7
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Change subject: smmstorev2: Load the communication buffer at SMM setup
......................................................................
Patch Set 6:
(2 comments)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/79738/comment/303d52f9_7f022132 :
PS6, Line 11: include <smmstore.h>
> Alphabetical order ?
Done
File src/drivers/smmstore/store.c:
https://review.coreboot.org/c/coreboot/+/79738/comment/a8ea04a3_3f86cc81 :
PS6, Line 10: #include <cpu/x86/smm.h>
> Alphabetical order ?
Done
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Change subject: [NOTFORMERGE]soc/amd/picasso: Add microcode binaries in PSP image
......................................................................
Abandoned
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Change subject: soc/intel/alderlake: Include ADL-N ID 5
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80166/comment/0daa8946_572b7958 :
PS8, Line 7: mb/intel/adlrvp
> Replace it with `soc/intel/alderlake`. […]
Done
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Change subject: soc/intel/alderlake: Include ADL-N ID 5
......................................................................
soc/intel/alderlake: Include ADL-N ID 5
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
---
M src/soc/intel/alderlake/vr_config.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/80166/9
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Link ramstage in one step
......................................................................
arch/x86: Link ramstage in one step
We only use the bfd linker currently but partial linking is not
supported by other linkers and is also a problem for LTO.
Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.mk
1 file changed, 3 insertions(+), 9 deletions(-)
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
Patch Set 3:
(1 comment)
File src/lib/lzmadecode.h:
https://review.coreboot.org/c/coreboot/+/70175/comment/62e6c0f7_f310df93 :
PS3, Line 28: typedef unsigned long int SizeT;
> also shouldn't this rather be size_t?
Done
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Hello Julius Werner, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
lib/lzmadecode: Allow for 8 byte reads on 64bit
This adds an optimization to lzma decode to also read from the boot
medium in chunks of 8 bytes if that is the general purpose register
length instead of always 4 bytes. It depends on the cache / memory / spi
controller whether this is faster, but it's likely to be either the same
or faster.
TESTED
- google/vilboz: cached boot medium
64bit before - 32bit - 64bit after
load FSP-M: 35,674 - 35,595 - 34,690
load ramstage: 42,134 - 43,378 - 40,882
load FSP-S: 24,954 - 25,496 - 24,368
- foxconn/g41m: uncached boot medium for testing
64bit before - 32bit - 64bit after
load ramstage: 51,164 - 51,872 - 51,894
Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/lib/lzmadecode.c
M src/lib/lzmadecode.h
2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/70175/4
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