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Change subject: vendorcode/cavium: Fix bitfields with signed integers
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Just wondering, how did you notice? Isn't the code compiled by the CI and there should be errors?
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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
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Change subject: acpi: Move HPET generation to a common location
......................................................................
Patch Set 10:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76128/comment/ee60d438_f069b207 :
PS9, Line 1266: #endif
> > A `static inline` with these guards in the header file at the forward […]
Hmmm, wouldn't be exactly inline anymore. But I guess it would work
and have the same cosmetic effect.
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Change subject: Makefile.inc: Compress DSDT file
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Makefile.inc: Compress DSDT file
Now that x86 has a CBFS cache we can use that cache as a DSDT ACPI table
decompression location. To be on the safe side, increase the cache size
to 64K which would largely fit all dsdt in coreboot.
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Change subject: Makefile.inc: Compress DSDT file
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75905/comment/a47a0e12_e12c436a :
PS4, Line 9: dsdt
> `s/dsdt/DSDT ACPI table/`
Done
https://review.coreboot.org/c/coreboot/+/75905/comment/e7f88285_4826cef3 :
PS4, Line 11: 128K
> I believe you meant 64 KiB.
Done
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75905/comment/3391b7da_b36e972a :
PS4, Line 300: LZMA
> We have been using lower case for compression algorithm in most places according to `grep` so I woul […]
Done
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Change subject: Makefile.inc: Compress DSDT file
......................................................................
Makefile.inc: Compress DSDT file
Now that x86 has a CBFS cache we can use that cache as a dsdt
decompression location. To be on the safe side, increase the cache size
to 64K which would largely fit all dsdt in coreboot.
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Change subject: Makefile.inc: Compress DSDT file
......................................................................
Makefile.inc: Compress DSDT file
Now that x86 has a CBFS cache we can use that cache as a dsdt
decompression location. To be on the safe side, increase the cache size
to 64K which would largely fit all dsdt in coreboot.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I3f555b1761c7ef4943d8de447ab299684403214b
---
M Makefile.mk
M src/arch/x86/Kconfig
2 files changed, 2 insertions(+), 2 deletions(-)
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Change subject: vendorcode/cavium: Fix bitfields with signed integers
......................................................................
vendorcode/cavium: Fix bitfields with signed integers
Bitfields with signed integers are not valid C code. This fixes
compilation with clang v16.0.6.
Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/80638/1
diff --git a/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h b/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h
index b77aa2a..499a6a4 100644
--- a/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h
+++ b/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h
@@ -113,8 +113,8 @@
uint64_t reserved2 : 32;
unsigned speed : 24;
unsigned lanes : 6;
- int full_duplex : 1;
- int up : 1;
+ unsigned full_duplex : 1;
+ unsigned up : 1;
} s;
} bdk_if_link_t;
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Change subject: arch/arm/armv{4,7}/Makefile.inc: Add more finegrained ld-ccopts
......................................................................
arch/arm/armv{4,7}/Makefile.inc: Add more finegrained ld-ccopts
Add linker targets only to stages when ARCH_#stage_ARMV{4,7} is set.
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