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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
Patch Set 5: Code-Review+1
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Hello Cliff Huang, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Jeff Daly, Kyösti Mälkki, Lance Zhao, Matt DeVillier, Nico Huber, Raul Rangel, Tim Wawrzynczak, Vanessa Eusebio, build bot (Jenkins),
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Change subject: acpi: Move HPET generation to a common location
......................................................................
acpi: Move HPET generation to a common location
HPET is usually a feature of the hardware that needs no runtime to check
whether it is present or it is typically unconditionally
enabled. This means a simple Kconfig option to generate the ACPI tables
is sufficient, which allows reduction of boilerplate.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I38b9962a8d568267356256a3edc51348b9417e20
---
M src/acpi/Kconfig
M src/acpi/Makefile.mk
M src/acpi/acpi.c
M src/acpi/acpi_hpet.c
M src/include/acpi/acpi.h
M src/soc/amd/common/block/acpi/Kconfig
M src/soc/amd/common/block/acpi/Makefile.mk
M src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/include/amdblocks/acpi.h
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi.c
M src/soc/intel/broadwell/pch/Kconfig
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/acpi.c
M src/southbridge/amd/pi/hudson/Kconfig
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/Kconfig
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/lpc.c
37 files changed, 45 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/76128/11
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Change subject: acpi: Move HPET generation to a common location
......................................................................
Patch Set 10:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76128/comment/4933dbaa_054a98bc :
PS9, Line 1266: #endif
> Hmmm, wouldn't be exactly inline anymore. But I guess it would work
> and have the same cosmetic effect.
Hmm I'm surprised the compiler is happy to do that... Inline is just a suggestion I suppose?
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Hello Julius Werner, Martin L Roth, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm/Kconfig
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/rockchip/rk3288/Kconfig
4 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/15
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80330?usp=email )
Change subject: arch/x86/ioapic: always write IOAPIC ID in set_ioapic_id
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80330/comment/3f56bb4c_e12c3e5b :
PS3, Line 18: The only
: southbridge that doesn't call register_new_ioapic_gsi0
> Which one is it?
sb/intel/i82371eb
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Change subject: mb/amd/birman_plus: Add Birman+ board support for Phoenix SOC
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS13:
> some files have comments that say that those should be updated for birman; maybe change that to birm […]
sure Felix, I will address these comments in future in different PRs.
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
lib/lzmadecode: Allow for 8 byte reads on 64bit
This adds an optimization to lzma decode to also read from the boot
medium in chunks of 8 bytes if that is the general purpose register
length instead of always 4 bytes. It depends on the cache / memory / spi
controller whether this is faster, but it's likely to be either the same
or faster.
TESTED
- google/vilboz: cached boot medium
64bit before - 32bit - 64bit after
load FSP-M: 35,674 - 35,595 - 34,690
load ramstage: 42,134 - 43,378 - 40,882
load FSP-S: 24,954 - 25,496 - 24,368
- foxconn/g41m: uncached boot medium for testing
64bit before - 32bit - 64bit after
load ramstage: 51,164 - 51,872 - 51,894
Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/lib/lzmadecode.c
M src/lib/lzmadecode.h
2 files changed, 12 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/70175/5
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
Patch Set 4:
(1 comment)
File src/lib/lzmadecode.h:
https://review.coreboot.org/c/coreboot/+/70175/comment/db25360d_4e6c7b24 :
PS4, Line 24:
> including types. […]
Done
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Change subject: mb/google/rex/var/deku: Refactor SSD power sequencing
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@Eran, please test this CL if u have any way to verify Deku
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Hello build bot (Jenkins),
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Change subject: soc/qualcomm/sc7{1,2}80: Increase romstage/verstage section for clang
......................................................................
soc/qualcomm/sc7{1,2}80: Increase romstage/verstage section for clang
Clang builds slightly larger binaries so increase the section.
Change-Id: Ide01233f209613678c5408f1afab19415c1071be
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/qualcomm/sc7180/memlayout.ld
M src/soc/qualcomm/sc7280/memlayout.ld
2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80639/3
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ide01233f209613678c5408f1afab19415c1071be
Gerrit-Change-Number: 80639
Gerrit-PatchSet: 3
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