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Change subject: arch/x86: Link ramstage in one step
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> need rebase
Done
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Hello Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
soc/intel/xeon_sp: Align resources to 4K
The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR 1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR 1 MiB
- VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/include/soc/iomap.h
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80548/3
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Hello Julius Werner, Martin L Roth, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#18).
Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm/Kconfig
M src/soc/nvidia/tegra124/Kconfig
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/rockchip/rk3288/Kconfig
5 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/18
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80598?usp=email )
Change subject: device/pnp_device: Skip init on disabled functions
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80598/comment/ae2dffcf_e9de1276 :
PS1, Line 15: in the log / don't cause any errors.
> So these 'decode base 0' prints are from `soc/intel/common/block/lpc`. […]
implemented in CB:80646
File src/device/pnp_device.c:
https://review.coreboot.org/c/coreboot/+/80598/comment/8ef1edcb_52b314a3 :
PS1, Line 403: dev->ops = ops;
> Dunno. That was just an example from the top of my head. It's […]
I'm not aware that it fixes any issue outside of the errors from the LPC PMIO function, so can address it there instead as linked above
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80601?usp=email )
Change subject: mb/purism/librem_cnl/var/librem_mini: Set RTC register defaults
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/80601/comment/acf4446a_3d21da54 :
PS2, Line 154: io 0x60 = 0x070
> I'm not sure if 0 isn't just a valid value for coreboot. Looking at the […]
alternately, can do CB:80645 instead
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80647?usp=email )
Change subject: soc/intel/common/lpc_lib: Demote printk for IO base value 0
......................................................................
soc/intel/common/lpc_lib: Demote printk for IO base value 0
An IO base of 0 set for a LPC-attached PNP device is more likely a sign
that the IO register is unused than an error, so demote the printk
message from ERROR to SPEW and adjust the text accordingly.
TEST=build/boot purism/librem_cnl (Mini v2), verify no errors in cbmem
log for unused registers in the SIO RTC.
Change-Id: I593f8e3c7eb9e877f89568fd63eabe12bb777f93
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/common/block/lpc/lpc_lib.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/80647/1
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index ed76049..6ca5c12 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -76,7 +76,7 @@
switch (base) {
case 0:
- printk(BIOS_ERR, "LPC IO decode base 0!\n");
+ printk(BIOS_SPEW, "LPC IO decode base 0; skipping\n");
return;
case 0x2e:
case 0x2f:
--
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Change subject: soc/intel/common/lpc: Skip setting resources for disabled devices
......................................................................
soc/intel/common/lpc: Skip setting resources for disabled devices
If a downstream LPC device (eg, SIO function) is disabled, we shouldn't
attempt to open PMIO windows for it, as those functions often have
unset IO bases (which default to 0), resulting in false errors like:
[ERROR] LPC IO decode base 0!
TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors
in cbmem log for disabled SIO functions.
Change-Id: I92c79fc01be21466976f3056242f6d1824878eab
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/common/block/lpc/lpc.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80646/1
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index dbd982b..b27e09e9 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -87,6 +87,9 @@
{
struct resource *res;
+ if (!dev->enabled)
+ return;
+
for (res = dev->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_IO)
lpc_open_pmio_window(res->base, res->size);
--
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