coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: arch/x86: Link ramstage in one step
by Jérémy Compostella (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Arthur Heymans. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71910?usp=email ) Change subject: arch/x86: Link ramstage in one step ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d Gerrit-Change-Number: 71910 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 20 Feb 2024 16:35:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.inc: Compress DSDT file
by Elyes Haouas (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Martin L Roth, Subrata Banik. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75905?usp=email ) Change subject: Makefile.inc: Compress DSDT file ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75905/comment/39256ec0_19238ca7 : PS7, Line 7: inc .mk -- To view, visit https://review.coreboot.org/c/coreboot/+/75905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f555b1761c7ef4943d8de447ab299684403214b Gerrit-Change-Number: 75905 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 20 Feb 2024 16:23:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Align resources to 4K
by Patrick Rudolph (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80548?usp=email ) Change subject: soc/intel/xeon_sp: Align resources to 4K ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > need rebase Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Gerrit-Change-Number: 80548 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 20 Feb 2024 16:17:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Align resources to 4K
by Patrick Rudolph (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80548?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Align resources to 4K ...................................................................... soc/intel/xeon_sp: Align resources to 4K The lower bit of the BAR might be used for something else, like enable bits, so mask the lower 12 bits and align all base address to 4K. Confirmed that all BARs have a minimum alignment of 4K, so that masking the lower bits doesn't change the reported address. The alignment of the VTD BARs is: - VTD_MMCFG_BASE_CSR 64 MiB - VTD_MMIOL_CSR 1 MiB - VTD_NCMEM_BASE_CSR 64 MiB - VTD_TSEG_BASE_CSR 1 MiB - VTD_BAR_CSR 4 KiB Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/uncore.c 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80548/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Gerrit-Change-Number: 80548 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
by Elyes Haouas (Code Review) 20 Feb '24

20 Feb '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80648?usp=email ) Change subject: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3 ...................................................................... crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3 Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum A util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80648/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e90117c..9470fe3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -43,7 +43,7 @@ IASL_VERSION="R06_28_23" # CLANG version number CLANG_VERSION=17.0.6 -CMAKE_VERSION=3.27.7 +CMAKE_VERSION=3.28.3 NASM_VERSION=2.16.01 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum b/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum deleted file mode 100644 index 691bc61..0000000 --- a/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -1b170ceae7fc9659b2cad7e1d8121b370acd5cf2 tarballs/cmake-3.27.7.tar.gz diff --git a/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum new file mode 100644 index 0000000..dc518a9 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum @@ -0,0 +1 @@ +cf332727ac863cc0c86ac4f8cd3b711d05a5e417 tarballs/cmake-3.28.3.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/80648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Gerrit-Change-Number: 80648 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: arch/arm: Build test all arm targets with clang
by Arthur Heymans (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Paul Menzel. Hello Julius Werner, Martin L Roth, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69747?usp=email to look at the new patch set (#18). Change subject: arch/arm: Build test all arm targets with clang ...................................................................... arch/arm: Build test all arm targets with clang Some targets cannot be supported by clang as clang generates slightly larger binaries which the hardware won't accept. Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/arm/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/rockchip/rk3288/Kconfig 5 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/69747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8 Gerrit-Change-Number: 69747 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: device/pnp_device: Skip init on disabled functions
by Matt DeVillier (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80598?usp=email ) Change subject: device/pnp_device: Skip init on disabled functions ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80598/comment/ae2dffcf_e9de1276 : PS1, Line 15: in the log / don't cause any errors. > So these 'decode base 0' prints are from `soc/intel/common/block/lpc`. […] implemented in CB:80646 File src/device/pnp_device.c: https://review.coreboot.org/c/coreboot/+/80598/comment/8ef1edcb_52b314a3 : PS1, Line 403: dev->ops = ops; > Dunno. That was just an example from the top of my head. It's […] I'm not aware that it fixes any issue outside of the errors from the LPC PMIO function, so can address it there instead as linked above -- To view, visit https://review.coreboot.org/c/coreboot/+/80598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c9d5cf34947535bf249b91f78d6fabfb28729ea Gerrit-Change-Number: 80598 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 20 Feb 2024 16:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl/var/librem_mini: Set RTC register defaults
by Matt DeVillier (Code Review) 20 Feb '24

20 Feb '24

Attention is currently required from: Jonathon Hall, Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80601?usp=email ) Change subject: mb/purism/librem_cnl/var/librem_mini: Set RTC register defaults ...................................................................... Patch Set 2: (1 comment) File src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb: https://review.coreboot.org/c/coreboot/+/80601/comment/acf4446a_3d21da54 : PS2, Line 154: io 0x60 = 0x070 > I'm not sure if 0 isn't just a valid value for coreboot. Looking at the […] alternately, can do CB:80645 instead -- To view, visit https://review.coreboot.org/c/coreboot/+/80601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I310a834a1fa7b8428879fbc160e4aae0a519e063 Gerrit-Change-Number: 80601 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Tue, 20 Feb 2024 16:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/common/lpc_lib: Demote printk for IO base value 0
by Matt DeVillier (Code Review) 20 Feb '24

20 Feb '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80647?usp=email ) Change subject: soc/intel/common/lpc_lib: Demote printk for IO base value 0 ...................................................................... soc/intel/common/lpc_lib: Demote printk for IO base value 0 An IO base of 0 set for a LPC-attached PNP device is more likely a sign that the IO register is unused than an error, so demote the printk message from ERROR to SPEW and adjust the text accordingly. TEST=build/boot purism/librem_cnl (Mini v2), verify no errors in cbmem log for unused registers in the SIO RTC. Change-Id: I593f8e3c7eb9e877f89568fd63eabe12bb777f93 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/lpc/lpc_lib.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/80647/1 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ed76049..6ca5c12 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -76,7 +76,7 @@ switch (base) { case 0: - printk(BIOS_ERR, "LPC IO decode base 0!\n"); + printk(BIOS_SPEW, "LPC IO decode base 0; skipping\n"); return; case 0x2e: case 0x2f: -- To view, visit https://review.coreboot.org/c/coreboot/+/80647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I593f8e3c7eb9e877f89568fd63eabe12bb777f93 Gerrit-Change-Number: 80647 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/common/lpc: Skip setting resources for disabled devices
by Matt DeVillier (Code Review) 20 Feb '24

20 Feb '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80646?usp=email ) Change subject: soc/intel/common/lpc: Skip setting resources for disabled devices ...................................................................... soc/intel/common/lpc: Skip setting resources for disabled devices If a downstream LPC device (eg, SIO function) is disabled, we shouldn't attempt to open PMIO windows for it, as those functions often have unset IO bases (which default to 0), resulting in false errors like: [ERROR] LPC IO decode base 0! TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors in cbmem log for disabled SIO functions. Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/lpc/lpc.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80646/1 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index dbd982b..b27e09e9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -87,6 +87,9 @@ { struct resource *res; + if (!dev->enabled) + return; + for (res = dev->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_IO) lpc_open_pmio_window(res->base, res->size); -- To view, visit https://review.coreboot.org/c/coreboot/+/80646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Gerrit-Change-Number: 80646 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2024