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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: configs: add ASUS A88XM-E sample configuration
......................................................................
configs: add ASUS A88XM-E sample configuration
This sample .config can be used ONLY if your git clone'd (and also
git reset --hard to the revision mentioned at restore_agesa.sh script)
coreboot source code has been processed with the following scripts:
restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/79838
csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
After you have executed the scripts above, you can use this .config
as the base config for your A88XM-E by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! I.e. if you are
using a SSD, you may want to change the "CONFIG_HUDSON_SATA_MODE"
from "0: NATIVE" to "2: AHCI". Also, I have disabled the Intel WiFi
at this .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ).
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Ie180e498a90d8a1c8380f18c77c5a6be0a731c2c
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A configs/config.asus_a88xm-e
1 file changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/79841/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79839?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches)
......................................................................
configs: add Lenovo G505S sample configuration (use with dGPU patches)
This sample .config can be used ONLY if your git clone'd (and also
git reset --hard to the revision mentioned at restore_agesa.sh script)
coreboot source code has been processed with the following scripts:
restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/79838
csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
After you have executed the scripts above, you can use this .config
as the base config for your G505S by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! I.e. it specifies
CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
which is compatible with R5-M230 dGPU, but if your G505S has HD-8570M
discrete GPU instead - you will need to change these configs to ",6663".
Or, if your G505S does not have a discrete GPU at all, please disable
CONFIG_AMD_DGPU_WITHOUT_EEPROM=y
and those DGPU configs will be disabled. Also, if you are using a SSD -
may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to
"2: AHCI". Also I've disabled the Intel WiFi at my .config to save space
( CONFIG_DRIVERS_INTEL_WIFI is not set ).
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Id7d07303d98f795ca699d1955574a01dc9c87d1a
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A configs/config.lenovo_g505s_use_with_dgpu_patches
1 file changed, 691 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79839/3
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80179?usp=email )
Change subject: i2c/drivers/generic: Add support for including a rotation matrix
......................................................................
Patch Set 6:
(1 comment)
File src/drivers/i2c/generic/chip.h:
https://review.coreboot.org/c/coreboot/+/80179/comment/d1656ae0_e1cd4a30 :
PS4, Line 81: int
> Sorry, so change it back - and then separate patch to switch them both to bools?
no, i'd use bool for has_rotation_matrix righ taway and change the other ones in a follow-up
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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email )
Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
Patch Set 4:
(2 comments)
File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/80579/comment/d9b7a62e_e20cf06d :
PS4, Line 118: _fspm_heap = .;
> Need to use ABSOLUTE(. […]
Can't this be simplified using `REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 4)` inside the section definition ?
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80579/comment/7bd62c25_b9a5d7b9 :
PS4, Line 227: there
s/there/the
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Attention is currently required from: Julius Werner.
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+2 by Julius Werner
Change subject: arch/arm64: Add Clang as supported target
......................................................................
arch/arm64: Add Clang as supported target
QEMU aarch64 boots to payload when compiled with clang.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm64/Kconfig
M src/soc/qualcomm/sc7180/Kconfig
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74501/22
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Hello Julius Werner, Martin L Roth, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69747?usp=email
to look at the new patch set (#19).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm/Kconfig
M src/soc/nvidia/tegra124/Kconfig
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/rockchip/rk3288/Kconfig
5 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/19
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Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80649?usp=email )
Change subject: Update chromeec submodule to upstream main
......................................................................
Update chromeec submodule to upstream main
Updating from commit id e486b388a7:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
to commit id 16b038ac70:
2024-02-20 13:58:44 +0000 - (ec_features: Enable RWSIG feature if CONFIG_PLATFORM_EC_RWSIG is set)
This brings in 12108 new commits.
Change-Id: Ie5b22057f52d66c1334d5ddcbd516e352a861441
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M 3rdparty/chromeec
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80649/1
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index e486b38..16b038a 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit e486b388a73f1e19f3142774d0b3ee166e8f41ff
+Subproject commit 16b038ac7000727713941e5b8e3cc1c9e1831049
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Change subject: arch/x86/*.ld: Use MEMORY command to verify sections
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
I like this idea.
File src/arch/x86/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/71871/comment/05006038_0bc1752c :
PS5, Line 22:
Unnecessary extra line break
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