coreboot-gerrit November 2024

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Correct board version in variant_device...
by Karthik Ramasubramanian (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Derek Huang, Paul Menzel, Robert Chen, Shou-Chieh Hsu. Karthik Ramasubramanian has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/84953?usp=email ) Change subject: mb/google/dedede/var/drawcia: Correct board version in variant_devicetree_update ...................................................................... Patch Set 11: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84953/comment/a45c1a08_fa901857?us… : PS11, Line 11: more board added after that. Specific Drawper board version as 0xa, 0xb and 0xf. > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. File src/mainboard/google/dedede/variants/drawcia/ramstage.c: https://review.coreboot.org/c/coreboot/+/84953/comment/6c113bdc_2efa70a9?us… : PS11, Line 37: /* Remove power IC after board version 0xc */ Please move this comment above the if condition. Also please add a comment regarding which Draw* variants have board version > b? Drawlat, Drawman, Drawcia, Drawper, anything else etc.? https://review.coreboot.org/c/coreboot/+/84953/comment/e48539b5_06fd0fbf?us… : PS11, Line 42: /* board version 0xa, 0xb , 0xf is for drawper unit */ Please move this comment above the if condition. Also please rephrase the comment as: `/* Board version 0xa, 0xb and 0xf are for Drawper units */` -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 11 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 04 Nov 2024 18:05:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/google/chromeec: Add is_battery_present()
by Karthik Ramasubramanian (Code Review) 04 Nov '24

04 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83735?usp=email ) Change subject: ec/google/chromeec: Add is_battery_present() ...................................................................... ec/google/chromeec: Add is_battery_present() This patch adds is_battery_present() to check if the battery is physically present BUG=b:335046538,b:329722827 TEST=Build Brox and check is_battery_present returns the correct battery status. Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83735 Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 24 insertions(+), 0 deletions(-) Approvals: Caveh Jalali: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 088f2fe..2ef2ea9 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1566,3 +1566,19 @@ return false; } + +bool google_chromeec_is_battery_present(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) { + /* Check if battery is present */ + if (resp.flags & EC_BATT_FLAG_BATT_PRESENT) + return true; + } + + return false; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 0062df6..20b508c 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -425,6 +425,14 @@ bool google_chromeec_is_battery_present_and_above_critical_threshold(void); /** + * Check if battery is present. + * + * @return true: if the battery is present + * false: if the battery is not present + */ +bool google_chromeec_is_battery_present(void); + +/** * Determine if the UCSI stack is currently active. * * @return true if EC implements the UCSI stack -- To view, visit https://review.coreboot.org/c/coreboot/+/83735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Gerrit-Change-Number: 83735 Gerrit-PatchSet: 8 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Subrata Banik (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... soc/intel/alderlake: Optimize reset handling for non-UFS boot This patch optimizes the reset handling in the Alder Lake romstage while disabling the UFS controller in an uni-boot scenario (a unified AP firmware image can boot both UFS and non-UFS systems). It introduces a check in `mainboard_expects_another_reset()` to skip unnecessary resets when a CSE slot switch is due, meaning CSE is not booting from the RW slot. This saves one reset for non-UFS SKUs when a CSE slot switch is pending. The patch also relocates the `cse_fw_sync()` call after disabling the UFS controllers to ensure the system reset flow can be better optimized and combined with any expected resets due to CSE synchronization. TEST=Able to build google/trulo eMMC sku and able to save one reset. Without this patch: 1. Warm reset after disabling UFS (1st reset) 2. Global reset after CSE sync (2nd reset) 3. Warm reset after disabling UFS (3rd reset) 4. Boot to OS With this patch: 1. Skip disabling UFS if CSE sync is due, aka no reset. 2. Global reset after CSE sync (1st reset) 3. CSE is booting from slot RW meaning CSE sync is done, perform UFS disabling and issue a warm reset after disabling UFS (2nd reset) 4. Boot to OS Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84996/1 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3acd2fd..d2abaee 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -34,7 +34,19 @@ bool __weak mainboard_expects_another_reset(void) { - return false; + bool reset_pending = true; + + if (!CONFIG(SOC_INTEL_CSE_LITE_SKU)) + reset_pending = false; + + /* + * Skip reset if CSE slot switch is pending meaning, CSE is booting from RO. + * CSE state switch will issue a reset anyway. + */ + if (is_cse_boot_to_rw() == true) + reset_pending = false; + + return reset_pending; } static void disable_ufs(void) @@ -182,9 +194,6 @@ if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) - cse_fw_sync(); - /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { @@ -196,6 +205,9 @@ } } + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) + cse_fw_sync(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: soc/intel/cmn/block/cse: Add API to check the current boot partition
by Subrata Banik (Code Review) 04 Nov '24

04 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84995?usp=email ) Change subject: soc/intel/cmn/block/cse: Add API to check the current boot partition ...................................................................... soc/intel/cmn/block/cse: Add API to check the current boot partition This patch introduces an API to check whether CSE is booting from the RW slot. This information can be used to determine if a CSE firmware update is pending, which would help to optimize the boot flow by knowing if any reset is expected due to CSE sync. TEST=Able to build google/brox. Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84995/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c5f0560..09281ab 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1071,6 +1071,19 @@ return !!cse_compare_sub_part_version(&cbfs_rw_version, cse_get_rw_version()); } +bool is_cse_boot_to_rw(void) +{ + if (cse_get_bp_info() != CB_SUCCESS) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); + return false; + } + + if (cse_get_current_bp() == RW) + return true; + + return false; +} + static uint8_t cse_fw_update(void) { struct region_device target_rdev; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 552eb7b..c97e4ec 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -611,4 +611,11 @@ * Returns true if an update is required, false otherwise */ bool is_cse_fw_update_required(void); + +/* + * Check if the CSE firmware is booting from RW slot. + * Returns true if CSE is booting from RW slot, false otherwise + */ +bool is_cse_boot_to_rw(void); + #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/84995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Gerrit-Change-Number: 84995 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Configure Acoustic noise mitigation
by Jayvik Desai (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Nick Vaccaro, Paul Menzel. Jayvik Desai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84908?usp=email ) Change subject: mb/google/nissa/var/riven: Configure Acoustic noise mitigation ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a Gerrit-Change-Number: 84908 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Nov 2024 13:31:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix uninitialized usb_cfg pointer
by Jayvik Desai (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Jayvik Desai has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84939?usp=email ) Change subject: soc/intel/alderlake: Fix uninitialized usb_cfg pointer ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Gerrit-Change-Number: 84939 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Nov 2024 13:21:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Disable UFS controllers only on S5 resume
by Jayvik Desai (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84974?usp=email ) Change subject: soc/intel/alderlake: Disable UFS controllers only on S5 resume ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84974?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf Gerrit-Change-Number: 84974 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Nov 2024 12:00:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Weimin Wu (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Eric Lai, Hualin Wei, Subrata Banik. Weimin Wu has posted comments on this change by Hualin Wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 3 Gerrit-Owner: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Nov 2024 11:37:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Hualin Wei (Code Review) 04 Nov '24

04 Nov '24

Attention is currently required from: Weimin Wu. Hualin Wei has posted comments on this change by Hualin Wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 3 Gerrit-Owner: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Nov 2024 11:35:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/cnvi: Add PRW for CNVi device
by Sean Rhodes (Code Review) 04 Nov '24

04 Nov '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84993?usp=email ) Change subject: soc/intel/common/cnvi: Add PRW for CNVi device ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b3dcdf7b6cdc32fb910e7a4783029076717beff Gerrit-Change-Number: 84993 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 04 Nov 2024 10:26:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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coreboot-gerrit November 2024