Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84949?usp=email )
Change subject: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
......................................................................
mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP
headers for FSP as banshee is using a converged firmware image.
This effort also helps to save banshee boot time by 80-100ms as
RPL FSP is better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which
saves 10ms of the boot time.
BUG=b:358254132
TEST=Able to build and boot google/banshee.
cold boot time w/o this CL
```
Total Time: 1,399,888
```
cold boot time w/ this CL
```
Total Time: 1,295,334
```
Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Dtrain Hsu: Looks good to me, approved
Subrata Banik: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2981ea7..20207f4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -169,6 +169,7 @@
select DRIVERS_GENERIC_GPIO_KEYS
select INTEL_GMA_HAVE_VBT
select MEMORY_SODIMM
+ select SOC_INTEL_RAPTORLAKE
config BOARD_GOOGLE_BRASK
select BOARD_GOOGLE_BASEBOARD_BRASK
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Change subject: mb/google/brox: Hint romstage init about upcoming reset
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Patchset:
PS8:
> I have edited the commit message right on gerrit (so there's no new code being pushed). […]
Awesome. Thank you.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel/jasperlake: add support for RP LTR mechanism
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84866/comment/f6b4e8d5_4681e85a?us… :
PS3, Line 13: Tested on Awasuki with RTL8852BE
> You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10].
Please add these details, and the command how to dump the root port configuration space.
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Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
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Patch Set 1: Code-Review+1
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Change subject: mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A
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