coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/common: Save dram_reserved_buffer info to sram
by Yu-Ping Wu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85123?usp=email ) Change subject: soc/mediatek/common: Save dram_reserved_buffer info to sram ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/85123/comment/3cbb1922_8503bb1a?us… : PS8, Line 359: reserved_buffer_ptr->dram_rank_num = curr_ddr_info->support_ranks; > mt8196/emi.c has been removed in CL*85098... […] Yup, create a new file mt8196/emi.c (or other name you prefer). -- To view, visit https://review.coreboot.org/c/coreboot/+/85123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc74103c3826a4de525e183e764aa1fd9ac2c131 Gerrit-Change-Number: 85123 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 09:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Update GPIO settings
by Tyler Wang (Code Review) 22 Nov '24

22 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85248?usp=email ) Change subject: mb/google/rex/var/kanix: Update GPIO settings ...................................................................... mb/google/rex/var/kanix: Update GPIO settings BUG=b:366291025 TEST=none Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/gpio.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85248/1 diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index 202dae6..a319429 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -56,8 +56,8 @@ PAD_NC(GPP_B03, NONE), /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ PAD_NC(GPP_B04, NONE), - /* GPP_B05 : [] ==> SPKR_INT_L_R */ - PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B05 : [] ==> SPKR_INT_L_R, test point */ + PAD_NC(GPP_B05, NONE), /* GPP_B06 : [] ==> HP_INT_L_R */ PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), /* GPP_B07 : [] ==> CAM_DET_L */ @@ -174,8 +174,8 @@ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), - /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, NONE), + /* GPP_D18 : [] ==> LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */ PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG), /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */ @@ -195,8 +195,8 @@ PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* GPP_E04 : [] ==> SOC_PEN_DETECT */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E04, NONE, PLTRST), + /* GPP_E04 : [] ==> SOC_PEN_DETECT, test point */ + PAD_NC(GPP_E04, NONE), /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ PAD_CFG_GPO(GPP_E05, 1, DEEP), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ @@ -320,9 +320,9 @@ PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), /* GPP_S01 : [] ==> SDW_HP_DATA_WLAN_PCM_SYNC */ PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), - /* GPP_S02 : [] ==> DMIC_SOC_CLK0_WLAN_PCM_OUT */ + /* GPP_S02 : [] ==> DMIC_CLK1_R */ PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), - /* GPP_S03 : [] ==> DMIC_SOC_DATA0_WLAN_PCM_IN */ + /* GPP_S03 : [] ==> DMIC_DATA1_R */ PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), /* GPP_S04 : Not connected. */ PAD_NC(GPP_S04, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/85248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7 Gerrit-Change-Number: 85248 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, V Sowmya, Vidya Gopalakrishnan, Vinay Kumar. Subrata Banik has posted comments on this change by Vidya Gopalakrishnan. ( https://review.coreboot.org/c/coreboot/+/85184?usp=email ) Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/trulo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85184/comment/65e6a3f3_ea1cb6b4?us… : PS4, Line 184: register "power_limits_config[ADL_N_041_6W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_7W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_15W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 35, : .tdp_pl4 = 83, : }" > > PL1/PL2 override hooks can still be used by ODMs by adding this block of code back. But overriding PL1/PL2 to a higher value as done here should not be a default guidance given from a reference design as using a higher PLx can have thermal impacts to silicon. This code block seems to be copied from some other production device variant that is also using a higher override for PLx values. Such overrides are not part of any other reference design variant. > > This code may coexist with the actual limit if there's a check to assert the build if the overridden value is larger than the limit. Ideally, a check like this should be included. > > There is no override required if overriden value is invalid or matches to the existing limit. we have agreed to implement an assert logic if overriden value is higher than the limit. -- To view, visit https://review.coreboot.org/c/coreboot/+/85184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a Gerrit-Change-Number: 85184 Gerrit-PatchSet: 5 Gerrit-Owner: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 08:53:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Save dram_reserved_buffer info to sram
by Crystal Guo (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Crystal Guo has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85123?usp=email ) Change subject: soc/mediatek/common: Save dram_reserved_buffer info to sram ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/85123/comment/c263fedb_d564a027?us… : PS8, Line 359: reserved_buffer_ptr->dram_rank_num = curr_ddr_info->support_ranks; > Thanks. […] mt8196/emi.c has been removed in CL*85098... Or create a new file to calculate the ranges? -- To view, visit https://review.coreboot.org/c/coreboot/+/85123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc74103c3826a4de525e183e764aa1fd9ac2c131 Gerrit-Change-Number: 85123 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 08:16:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Save dram_reserved_buffer info to sram
by Yu-Ping Wu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85123?usp=email ) Change subject: soc/mediatek/common: Save dram_reserved_buffer info to sram ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/85123/comment/80ca3b76_419f40c8?us… : PS8, Line 359: reserved_buffer_ptr->dram_rank_num = curr_ddr_info->support_ranks; > Yes, it works, thanks […] Thanks. Instead of calculating the ranges in `bootmem_platform_add_ranges`, please add an API in mt8196/emi.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/85123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc74103c3826a4de525e183e764aa1fd9ac2c131 Gerrit-Change-Number: 85123 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 08:12:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Yu-Ping Wu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Kenji Yu. Yu-Ping Wu has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... Patch Set 8: (1 comment) File soc/mediatek/mt8196/sspm_release_notes.txt: https://review.coreboot.org/c/blobs/+/85247/comment/03931bfd_b2863fd1?usp=e… : PS8, Line 4: Update sspm.bin to fix suspend issue. Fix suspend issue. -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 8 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 08:08:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Yu-Ping Wu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... Patch Set 5: (3 comments) File src/soc/mediatek/mt8196/bootblock.c: https://review.coreboot.org/c/coreboot/+/85188/comment/cc580518_48e6c4f9?us… : PS5, Line 19: mm_pre_init Why is this called `pre_init`? This only registers callbacks for 3 IDs. Looking at the code, I don't think we need to register them before `mt_pll_post_init`. The `disp_vcore_cb` callback in mtcmos.c is also registered in `mtcmos_post_init`, not in `pre_init` or `init` function. I wonder if we can rename this function to `mminfra_post_init`, and move the 3 `mtcmos_ctrl` calls there: ``` void mminfra_post_init(void) { mtcmos_cb_register(...); mtcmos_cb_register(...); mtcmos_cb_register(...); mtcmos_ctrl(MTCMOS_ID_MM_INFRA_AO, MTCMOS_POWER_ON); mtcmos_ctrl(MTCMOS_ID_MM_INFRA0, MTCMOS_POWER_ON); mtcmos_ctrl(MTCMOS_ID_MM_INFRA1, MTCMOS_POWER_ON); } ``` Then the flow here would be: ``` mtcmos_init(); mt_pll_post_init(); mminfra_post_init(); mtcmos_post_init(); ``` Does that make sense to you? File src/soc/mediatek/mt8196/include/soc/mminfra.h: https://review.coreboot.org/c/coreboot/+/85188/comment/5f27db01_8ff7fe78?us… : PS5, Line 33: mm mminfra File src/soc/mediatek/mt8196/mminfra_pd.c: PS5: If there's no other `mminfra_*.c` files, can we rename this to `mminfra.c`? -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 07:58:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yu-Ping Wu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 34: (2 comments) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/d293607f_9a5c4b58?us… : PS34, Line 390: if (!strcmp(item->name, cb->name)) { Using a string as the unique identifier is inefficient. If we really worry about having register duplicate callbacks, please use numeric IDs. However I'm not sure if the check is needed here. https://review.coreboot.org/c/coreboot/+/84497/comment/41651479_d3492d78?us… : PS34, Line 836: mtcmos_ctrl(MTCMOS_ID_MM_INFRA_AO, MTCMOS_POWER_ON); : mtcmos_ctrl(MTCMOS_ID_MM_INFRA0, MTCMOS_POWER_ON); : mtcmos_ctrl(MTCMOS_ID_MM_INFRA1, MTCMOS_POWER_ON); : : mtcmos_ctrl(MTCMOS_ID_DISP_VCORE, MTCMOS_POWER_ON); So, the whole callback code is only for these 4 `mtcmos_ctrl` calls? If there are no other calls that need callbacks, then we can remove the callback infrastructure altogether. ``` // spm_mtcmos.h struct mtcmos_ops { int (*pre_on)(void); int (*pre_off)(void); ... int (*post_on_sram)(void); }; // mtcmos.c void mtcmos_ctrl_ops(enum mtcmos_id id, enum mtcmos_state state, const struct mtcmos_ops *ops) { ...; } void mtcmos_ctrl(enum mtcmos_id id, enum mtcmos_state state) { mtcmos_ctrl_ops(id, state, NULL); } static struct mtcmos_ops disp_vcore_ops { ...; }; void mtcmos_post_init(void) { ... mtcmos_ctrl_ops(MTCMOS_ID_DISP_VCORE, MTCMOS_POWER_ON, &disp_vcore_ops); ... } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 34 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 07:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Yidi Lin (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Kenji Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/blobs/+/85247/comment/ab92af2d_6dc4925f?usp=e… : PS8, Line 9: Update sspm.bin to fix suspend issue. Can you elaborate the original suspend issue ? https://review.coreboot.org/c/blobs/+/85247/comment/d730c1d1_9df31631?usp=e… : PS8, Line 11: b:317009620 I don't think this is the correct bug ID. -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 8 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 07:28:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit November 2024