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Change subject: acpi.c: Guard FACS generation
......................................................................
acpi.c: Guard FACS generation
It's not expected that non-x86 arch implement x86 style sleep states and
resume.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3
---
M src/acpi/acpi.c
1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/76178/3
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76000?usp=email )
Change subject: acpi.c: Swap XSDT and RSDT for adding/finding tables
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76000/comment/d1646f4b_eea66b6d :
PS5, Line 16: never happens with x86 platforms.
> While we may fill XSDT, our S3 resume path ignores it. […]
Done
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75626?usp=email )
Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75626/comment/724ccbd2_ff4ca255 :
PS14, Line 186: m_cfg->GenerateNewTmeKey = 1;
Can you clarify - Shouldn't this be enabled even `else` scenario as well?
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Change subject: acpi.c: Add FACS and DSDT to debug hex printing
......................................................................
Patch Set 2:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76350/comment/9a7ee415_eb018857 :
PS1, Line 1943: acpidump_print(facs);
: acpidump_print(dsdt);
> shouldn't we check if the pointers are not NULL or would it be better to do that in acpidump_print? […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: acpi.c: Add FACS and DSDT to debug hex printing
......................................................................
acpi.c: Add FACS and DSDT to debug hex printing
TESTED acpixtract -a is able to extract all the dumped tables including
FACS and DSDT.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376
---
M src/acpi/acpi.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/76350/2
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Change subject: acpi: Add functions to declare ARM GIC V3 hardware
......................................................................
acpi: Add functions to declare ARM GIC V3 hardware
For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
---
M src/acpi/Kconfig
M src/acpi/acpi.c
A src/acpi/acpi_gic.c
M src/arch/arm64/Makefile.inc
M src/include/acpi/acpi.h
M src/include/device/path.h
6 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/76132/5
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Change subject: acpi: Add functions to declare ARM GIC V3 hardware
......................................................................
Patch Set 4:
(2 comments)
File src/acpi/acpi_gic.c:
https://review.coreboot.org/c/coreboot/+/76132/comment/b688203e_aa68f138 :
PS3, Line 20: gicc->gicr_base_address = 0; /* ignored by ASPM if GICR is present */
> `OSPM`
Done
https://review.coreboot.org/c/coreboot/+/76132/comment/d89e800a_bc39a989 :
PS3, Line 22: /* For platforms implementing ARMv8 the format must be:
: * Bits [63:40] Must be zero
: * Bits [39:32] Aff3 : Match Aff3 of target processor MPIDR
: * Bits [31:24] Must be zero
: * Bits [23:16] Aff2 : Match Aff2 of target processor MPIDR
: * Bits [15:8] Aff1 : Match Aff1 of target processor MPIDR
: * Bits [7:0] Aff0 : Match Aff0 of target processor MPIDR
: */
: gicc->mpidr = mpidr & 0xff00ffffff;
> is this comment for mpidr ? That mask value doesn't seem to match the comment?
I'm not sure what you mean?
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