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Hello Jakub Czapiga, Kapil Porwal, Ravishankar Sarawadi, Sridhar Siricilla, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
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Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize
when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDS
are programmed only when INTEL_TME is enabled.
Bug=b:276120526
TEST=Able to build REX platform.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/75626/15
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Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75626/comment/3406f849_f4929351 :
PS14, Line 190: Excluding CBMEM region from TME encryption and new key "
: "generation on warm boot not enabled
The control will reach here when the ram_top aka memory exclusion range is zero aka no range has been specified.
What is the expectation here ?
1. user doesn't want to exclude any memory range hence, the exclusion range is zero ?
2. passing exclusion range zero doesn't mean that SoC should stop creating new keys across reboots and skip security guideline?
As long as the `TME_KEY_REGENERATION_ON_WARM_BOOT` is set, the `m_cfg->GenerateNewTmeKey` should be also enabled
```
m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT);
if (m_cfg->GenerateNewTmeKey) {
uint32_t ram_top = get_ramtop_addr();
if (!ram_top) {
printk(BIOS_WARNIG, "Invalid exclusion range start address. Full memory encryption is enabled"\n");
return;
}
m_cfg->TmeExcludeBase = (ram_top - 16*MiB);
m_cfg->TmeExcludeSize = 16*MiB;
}
```
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Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> I have a https://us-store.msi. […]
There's currently no plans for us to add more to this.
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Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75626/comment/d0d3d9be_d044eb8f :
PS14, Line 186: m_cfg->GenerateNewTmeKey = 1;
> Can you clarify - Shouldn't this be enabled even `else` scenario as well?
I got the details from "https://review.coreboot.org/c/coreboot/+/76879/1" , please ignore the comment :)
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Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75626/comment/11bc00c6_222e6d90 :
PS14, Line 186: m_cfg->GenerateNewTmeKey = 1;
> Can you clarify - Shouldn't this be enabled even `else` scenario as well?
this should be outside if-else loop aka before line #185
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Change subject: acpi.c: Fill in >4G FADT entries correctly
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS3:
> Could you pull related CB:76000 on the same patchtrain, please?
Done
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Hello Felix Held, Lance Zhao, Nico Huber, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified-1 by build bot (Jenkins)
Change subject: acpi.c: Fill in >4G FADT entries correctly
......................................................................
acpi.c: Fill in >4G FADT entries correctly
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I84ab0068e8409a5e525ddc781347087680d80640
---
M src/acpi/acpi.c
1 file changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/76179/5
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