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Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Hi Derek, […]
Confirmed the CL working fine.
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Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables
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Patch Set 6: Code-Review+1
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Change subject: acpi: Add functions to declare ARM GIC V3 hardware
......................................................................
Patch Set 5:
(2 comments)
File src/arch/arm64/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/76132/comment/17e19521_689a091c :
PS5, Line 122: ramstage-$(CONFIG_ACPI_COMMON_MADT_GICC_V3) += ../../acpi/acpi_gic.c
Why put that here and not in acpi/Makefile.inc?
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/76132/comment/4c95182d_92a110c9 :
PS5, Line 1571: uintptr_t get_gicr_base(void);
These are platform callbacks, right? They should probably be a bit better namespaced, e.g. how about platform_get_gicd_base()?
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Change subject: amd/soc/common: Use relative offset for AMDFW
......................................................................
Patch Set 14:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72961/comment/5987e3e7_263174ee :
PS11, Line 12: TEST=binary identical test on amd/majolica amd/birman amd/mandolin
> Please add a blank line above.
Done
https://review.coreboot.org/c/coreboot/+/72961/comment/b99e4cee_b25580c4 :
PS11, Line 15: This is one of series of patches to support 32/64M flash.
> This commit is part of a series of patches to support 32/64M flash.
Done
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72961?usp=email
to look at the new patch set (#14).
The following approvals got outdated and were removed:
Code-Review+2 by Fred Reitberger, Verified+1 by build bot (Jenkins)
Change subject: amd/soc/common: Use relative offset for AMDFW
......................................................................
amd/soc/common: Use relative offset for AMDFW
The amdfw.rom is mostly in region COREBOOT. Calculate the relative
address as the CBFS module address. That is for future 32M flash size
support.
TEST=binary identical test on amd/birman amd/majolica amd/gardenia
amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon
pcengines/apu2
google/skyrim google/guybrush google/zork google/kahlee
This commit is part of a series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/common/Makefile.inc
1 file changed, 9 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/72961/14
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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
Patch Set 23:
(2 comments)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/72939/comment/5737d01f_8202bbe8 :
PS20, Line 82: default AMD_FWM_POSITION_20000 if !AMD_FWM_POSITION_420000_DEFAULT && \
: !AMD_FWM_POSITION_820000_DEFAULT && \
: !AMD_FWM_POSITION_C20000_DEFAULT && \
: !AMD_FWM_POSITION_E20000_DEFAULT && \
: !AMD_FWM_POSITION_F20000_DEFAULT && \
: !AMD_FWM_POSITION_FA0000_DEFAULT
: default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT
: default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT
: default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT
: default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT
: default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT
: default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT
:
> I think this can be simplified by flipping the order and just leaving the last entry as `default AMD […]
Done
File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/72939/comment/8451e37c_268257e7 :
PS21, Line 150: STONEYRIDGE_FWM_POSITION)
> Gardenia can not pass the identical test.
Done.
With https://review.coreboot.org/c/coreboot/+/76764, images smaller that 16M can pass the identical test.
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Change subject: arch/arm64: Hook up ACPI table generation
......................................................................
Patch Set 4:
(2 comments)
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/76071/comment/cdd08a8d_2d6753c8 :
PS4, Line 61: config MAX_ACPI_TABLE_SIZE_KB
I think this needs to be moved to some platform-independent place (e.g. src/acpi/Kconfig) if you want to use it here as well.
File src/arch/arm64/tables.c:
https://review.coreboot.org/c/coreboot/+/76071/comment/54fe7648_41a2a534 :
PS4, Line 18: printk(BIOS_ERR, "Increase ACPI size\n");
I see that this is the same as what x86 already does, but this is a truly terrible API. We're running straight over other CBMEM spaces and this isn't even an assert(), just a BIOS_ERR print. Can we (in a separate patch effort) fix write_acpi_tables() to actually take an upper bound and respect it?
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