coreboot-gerrit August 2023

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[L] Change in coreboot[master]: payloads/external/LinuxBoot: Clean up
by Maximilian Brune (Code Review) 02 Aug '23

02 Aug '23

Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76150?usp=email ) Change subject: payloads/external/LinuxBoot: Clean up ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > Which tree did you use to verify this patchset? […] The build directory refers to the build directory inside the Linuxboot directory and not the one in the coreboot root directory. But I think I see the culprit. Can you try this patch: CB:76914 -- To view, visit https://review.coreboot.org/c/coreboot/+/76150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e757108e0dd473969fe5a192ad0733f1fe6286 Gerrit-Change-Number: 76150 Gerrit-PatchSet: 10 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 23:48:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: payloads/external/Linuxboot/Makefile: Add build prerequisite
by Maximilian Brune (Code Review) 02 Aug '23

02 Aug '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76914?usp=email ) Change subject: payloads/external/Linuxboot/Makefile: Add build prerequisite ...................................................................... payloads/external/Linuxboot/Makefile: Add build prerequisite This adds a missing prerequisite, because otherwise it can happen that curl tries to put the downloaded kernel in a non existing build directory Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I459172f794ab9c1010cebcff5e28f1454e136fba --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/76914/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 4156e1e..01da40c 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -28,7 +28,7 @@ kernel_mirror_path := $(kernel_mirror)/v6.x endif -build/$(kernel_tarball).xz: +build/$(kernel_tarball).xz: | build echo " Test $(kernel_version)" echo " WWW $(kernel_mirror_path)/$(kernel_tarball).xz"; curl -OLSs --output-dir build "$(kernel_mirror_path)/$(kernel_tarball).xz"; -- To view, visit https://review.coreboot.org/c/coreboot/+/76914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I459172f794ab9c1010cebcff5e28f1454e136fba Gerrit-Change-Number: 76914 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ec/google/chromeec: move TBMC ACPI device under CREC
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Boris Mittelberg, Matt DeVillier, Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76792?usp=email ) Change subject: ec/google/chromeec: move TBMC ACPI device under CREC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4 Gerrit-Change-Number: 76792 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 23:43:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric_helper: use DF broadcast read/write functions
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76887?usp=email to look at the new patch set (#2). Change subject: soc/amd/common/data_fabric_helper: use DF broadcast read/write functions ...................................................................... soc/amd/common/data_fabric_helper: use DF broadcast read/write functions Instead of open coding the broadcast data fabric PCI register access in the functions for indirect non-broadcast data fabric register access, just use the existing data_fabric_broadcast_[read,write]32 functions. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/76887/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f Gerrit-Change-Number: 76887 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76889?usp=email ) Change subject: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_* ...................................................................... soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_* Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped form the define names. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 --- M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/data_fabric.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/76889/1 diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index ed0b456..9ee977f 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -85,7 +85,7 @@ } if (dram_base_reg & DRAM_BASE_HOLE_EN) { - dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL, + dram_hole_ctl = data_fabric_read32(DF_DRAM_HOLE_CTL, IOMS0_FABRIC_ID); hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); size_below_hole = hole_base - memory_base; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 93d3239..5926e49d 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -50,12 +50,12 @@ #define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) -#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) +#define DF_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) -#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110) +#define DF_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_INTLV_CH_SHFT 4 @@ -65,7 +65,7 @@ #define DRAM_BASE_ADDR_SHFT 12 #define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) -#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114) +#define DF_DRAM_LIMIT0 DF_REG_ID(0, 0x114) #define DRAM_LIMIT_DST_ID_SHFT 0 #define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 @@ -78,8 +78,8 @@ #define PICASSO_NUM_DRAM_REG 2 #define DF_DRAM_BASE(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ - + D18F0_DRAM_BASE0) + + DF_DRAM_BASE0) #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ - + D18F0_DRAM_LIMIT0) + + DF_DRAM_LIMIT0) #endif /* AMD_PICASSO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/76889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 Gerrit-Change-Number: 76889 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric_helper: use DF broadcast read/write functions
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

1 0

[M] Change in coreboot[master]: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76886?usp=email ) Change subject: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros ...................................................................... soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e --- M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h A src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/phoenix/include/soc/data_fabric.h M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/data_fabric.h 10 files changed, 98 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/76886/1 diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 3b1f588..100529e 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_CEZANNE_DATA_FABRIC_H #define AMD_CEZANNE_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) #define IOMS0_FABRIC_ID 10 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 1f0e2cf..b0b98ea 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -11,38 +11,41 @@ #include <soc/pci_devs.h> #include <types.h> -static void data_fabric_set_indirect_address(uint8_t func, uint16_t reg, uint8_t instance_id) +static void data_fabric_set_indirect_address(uint16_t fn_reg, uint8_t instance_id) { union df_ficaa ficaa = { .cfg_inst_acc_en = 1 }; /* target only specific instance */ /* convert register address to 32-bit register number */ - ficaa.reg_num = reg >> 2; - ficaa.func_num = func; + ficaa.reg_num = DF_REG_REG(fn_reg) >> 2; + ficaa.func_num = DF_REG_FN(fn_reg); ficaa.inst_id = instance_id; - pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, ficaa.raw); + pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAA_BIOS)), + DF_REG_REG(DF_FICAA_BIOS), ficaa.raw); } -uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id) +uint32_t data_fabric_read32(uint16_t fn_reg, uint8_t instance_id) { /* Broadcast reads might return unexpected results when a register has different contents in the different instances. */ if (instance_id == BROADCAST_FABRIC_ID) - return data_fabric_broadcast_read32(function, reg); + return data_fabric_broadcast_read32(fn_reg); /* non-broadcast data fabric accesses need to be done via indirect access */ - data_fabric_set_indirect_address(function, reg, instance_id); - return pci_read_config32(SOC_DF_F4_DEV, DF_FICAD_LO); + data_fabric_set_indirect_address(fn_reg, instance_id); + return pci_read_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAD_LO)), + DF_REG_REG(DF_FICAD_LO)); } -void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data) +void data_fabric_write32(uint16_t fn_reg, uint8_t instance_id, uint32_t data) { if (instance_id == BROADCAST_FABRIC_ID) { - data_fabric_broadcast_write32(function, reg, data); + data_fabric_broadcast_write32(fn_reg, data); return; } /* non-broadcast data fabric accesses need to be done via indirect access */ - data_fabric_set_indirect_address(function, reg, instance_id); - pci_write_config32(SOC_DF_F4_DEV, DF_FICAD_LO, data); + data_fabric_set_indirect_address(fn_reg, instance_id); + pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAD_LO)), + DF_REG_REG(DF_FICAD_LO), data); } void data_fabric_print_mmio_conf(void) @@ -53,12 +56,12 @@ "=== Data Fabric MMIO configuration registers ===\n" "idx base limit control R W NP F-ID\n"); for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - control.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); + control.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i)); /* Base and limit address registers don't contain the lower address bits, but are shifted by D18F0_MMIO_SHIFT bits */ - base = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_BASE(i)) + base = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_BASE(i)) << D18F0_MMIO_SHIFT; - limit = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i)) + limit = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_LIMIT(i)) << D18F0_MMIO_SHIFT; /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ limit += (1 << D18F0_MMIO_SHIFT) - 1; @@ -74,15 +77,15 @@ void data_fabric_disable_mmio_reg(unsigned int reg) { union df_mmio_control ctrl = { .fabric_id = IOMS0_FABRIC_ID }; - data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw); - data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), 0); - data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), 0); + data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw); + data_fabric_broadcast_write32(DF_MMIO_BASE(reg), 0); + data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), 0); } static bool is_mmio_reg_disabled(unsigned int reg) { union df_mmio_control ctrl; - ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(reg)); + ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(reg)); return !(ctrl.we || ctrl.re); } @@ -128,12 +131,12 @@ for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { /* Adjust all registers that overlap */ - ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); + ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i)); if (!(ctrl.we || ctrl.re)) continue; /* not enabled */ - base = data_fabric_broadcast_read32(0, DF_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i)); + base = data_fabric_broadcast_read32(DF_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(DF_MMIO_LIMIT(i)); if (base > np_top || limit < np_bot) continue; /* no overlap at all */ @@ -145,7 +148,7 @@ if (base < np_bot && limit > np_top) { /* Split the configured region */ - data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1); + data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1); reg = data_fabric_find_unused_mmio_reg(); if (reg < 0) { /* Although a pair could be freed later, this condition is @@ -154,17 +157,17 @@ printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); continue; } - data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw); + data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw); continue; } /* If still here, adjust only the base or limit */ if (base <= np_bot) - data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1); + data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1); else - data_fabric_broadcast_write32(0, DF_MMIO_BASE(i), np_top + 1); + data_fabric_broadcast_write32(DF_MMIO_BASE(i), np_top + 1); } reg = data_fabric_find_unused_mmio_reg(); @@ -175,9 +178,9 @@ union df_mmio_control np_ctrl = { .fabric_id = IOMS0_FABRIC_ID, .np = 1, .we = 1, .re = 1 }; - data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), np_ctrl.raw); + data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), np_ctrl.raw); data_fabric_print_mmio_conf(); } diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 1b33f31..f28bb12 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -38,8 +38,8 @@ static void data_fabric_get_mmio_base_size(unsigned int reg, resource_t *mmio_base, resource_t *mmio_limit) { - const uint32_t base_reg = data_fabric_broadcast_read32(0, DF_MMIO_BASE(reg)); - const uint32_t limit_reg = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(reg)); + const uint32_t base_reg = data_fabric_broadcast_read32(DF_MMIO_BASE(reg)); + const uint32_t limit_reg = data_fabric_broadcast_read32(DF_MMIO_LIMIT(reg)); /* The raw register values are bits 47..16 of the actual address */ *mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT; *mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1; @@ -101,7 +101,7 @@ (1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE; for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); + ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i)); /* Relevant MMIO regions need to have both reads and writes enabled */ if (!ctrl.we || !ctrl.re) diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 4fb28fc..1cebb26 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_DATA_FABRIC_H #define AMD_BLOCK_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <amdblocks/pci_devs.h> #include <device/pci_ops.h> #include <soc/data_fabric.h> @@ -24,21 +25,21 @@ /* Last 12GB of the usable address space are reserved */ #define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB) -uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); -void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); +uint32_t data_fabric_read32(uint16_t fn_reg, uint8_t instance_id); +void data_fabric_write32(uint16_t fn_reg, uint8_t instance_id, uint32_t data); static __always_inline -uint32_t data_fabric_broadcast_read32(uint8_t function, uint16_t reg) +uint32_t data_fabric_broadcast_read32(uint16_t fn_reg) { /* No bit masking required. Macros will apply mask to values. */ - return pci_read_config32(_SOC_DEV(DF_DEV, function), reg); + return pci_read_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_REG(fn_reg)); } static __always_inline -void data_fabric_broadcast_write32(uint8_t function, uint16_t reg, uint32_t data) +void data_fabric_broadcast_write32(uint16_t fn_reg, uint32_t data) { /* No bit masking required. Macros will apply mask to values. */ - pci_write_config32(_SOC_DEV(DF_DEV, function), reg, data); + pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_REG(fn_reg), data); } void data_fabric_print_mmio_conf(void); diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h b/src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h new file mode 100644 index 0000000..5e3bccd --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_DATA_FABRIC_DEFS_H +#define AMD_BLOCK_DATA_FABRIC_DEFS_H + +/* The DF register offset is only 11 bits with the two LSBs being 0. To be consistent with the + extended PCI config space size, 12 bits are used for the register offset. */ +#define DF_REG_ID(fn, reg) (((fn) & 0x7) << 12 | ((reg) & 0xfff)) +#define DF_REG_FN(id) (((id) >> 12) * 0x7) +#define DF_REG_REG(id) ((id) & 0xfff) + +#endif /* AMD_BLOCK_DATA_FABRIC_DEFS_H */ diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index c0482ee..3ddac62 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_GLINDA_DATA_FABRIC_H #define AMD_GLINDA_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0xD80 -#define D18F0_MMIO_LIMIT0 0xD84 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0xD88 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x8C -#define DF_FICAD_LO 0xB8 -#define DF_FICAD_HI 0xBC +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) #define IOMS0_FABRIC_ID 15 diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index c484cd1..ebcaf2b 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -3,13 +3,14 @@ #ifndef AMD_MENDOCINO_DATA_FABRIC_H #define AMD_MENDOCINO_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208) #if CONFIG(SOC_AMD_REMBRANDT) #define DF_MMIO_REG_SET_SIZE 3 @@ -19,9 +20,9 @@ #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) #define IOMS0_FABRIC_ID 9 diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h index 770c048..790b868 100644 --- a/src/soc/amd/phoenix/include/soc/data_fabric.h +++ b/src/soc/amd/phoenix/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_PHOENIX_DATA_FABRIC_H #define AMD_PHOENIX_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0xD80 -#define D18F0_MMIO_LIMIT0 0xD84 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0xD88 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x8C -#define DF_FICAD_LO 0xB8 -#define DF_FICAD_HI 0xBC +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) #define IOMS0_FABRIC_ID 0x13 diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 7482a03..ed0b456 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -64,10 +64,10 @@ for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; dram_map_idx++) { dram_base_reg = - data_fabric_read32(0, DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); + data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); if (dram_base_reg & DRAM_BASE_REG_VALID) { - dram_limit_reg = data_fabric_read32(0, DF_DRAM_LIMIT(dram_map_idx), + dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx), IOMS0_FABRIC_ID); memory_length = ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 @@ -85,7 +85,7 @@ } if (dram_base_reg & DRAM_BASE_HOLE_EN) { - dram_hole_ctl = data_fabric_read32(0, D18F0_DRAM_HOLE_CTL, + dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL, IOMS0_FABRIC_ID); hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); size_below_hole = hole_base - memory_base; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 4446371..382de8a 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_PICASSO_DATA_FABRIC_H #define AMD_PICASSO_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) #define IOMS0_FABRIC_ID 9 @@ -47,15 +48,15 @@ }; -#define D18F0_VGAEN 0x80 +#define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) -#define D18F0_DRAM_HOLE_CTL 0x104 +#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) -#define D18F0_DRAM_BASE0 0x110 +#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_INTLV_CH_SHFT 4 @@ -65,7 +66,7 @@ #define DRAM_BASE_ADDR_SHFT 12 #define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) -#define D18F0_DRAM_LIMIT0 0x114 +#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114) #define DRAM_LIMIT_DST_ID_SHFT 0 #define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Gerrit-Change-Number: 76886 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_en
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76885?usp=email ) Change subject: soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_en ...................................................................... soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_en Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76885/1 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index fb4b26c..1f0e2cf 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -13,7 +13,7 @@ static void data_fabric_set_indirect_address(uint8_t func, uint16_t reg, uint8_t instance_id) { - union df_ficaa ficaa = { .cfg_inst_acc_en = 1 }; + union df_ficaa ficaa = { .cfg_inst_acc_en = 1 }; /* target only specific instance */ /* convert register address to 32-bit register number */ ficaa.reg_num = reg >> 2; ficaa.func_num = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/76885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Gerrit-Change-Number: 76885 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: [WIP] util/crossgcc: Make Clang using Z3
by Martin L Roth (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Elyes Haouas, Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76421?usp=email ) Change subject: [WIP] util/crossgcc: Make Clang using Z3 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76421/comment/ee2806a4_bc6148a2 : PS2, Line 7: [WIP] Please use the "Mark as Work in Progress" button in the menu at the top right of the change. This lets the search filter exclude it from searches. -- To view, visit https://review.coreboot.org/c/coreboot/+/76421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1363ea8f96911bcffcf9b85a2e42d77e850fb9e9 Gerrit-Change-Number: 76421 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Aug 2023 23:11:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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