coreboot-gerrit August 2023

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[M] Change in coreboot[master]: mb/google/nissa/var/pirrha: Add GPIO table
by SH Kim (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Derek Huang, Shou-Chieh Hsu, Tarun Tuli. Hello Derek Huang, Shou-Chieh Hsu, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76882?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/pirrha: Add GPIO table ...................................................................... mb/google/nissa/var/pirrha: Add GPIO table Add GPIO table for Pirrha. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- A src/mainboard/google/brya/variants/pirrha/Makefile.inc A src/mainboard/google/brya/variants/pirrha/gpio.c 2 files changed, 125 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76882/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d Gerrit-Change-Number: 76882 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: acpi.c: Find FACS using 64bit address fields
by Lean Sheng Tan (Code Review) 03 Aug '23

03 Aug '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76293?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: acpi.c: Find FACS using 64bit address fields ...................................................................... acpi.c: Find FACS using 64bit address fields Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Lean Sheng Tan: Looks good to me, approved Kyösti Mälkki: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 07ca408..c385b58 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1599,7 +1599,8 @@ } printk(BIOS_DEBUG, "FADT found at %p\n", fadt); - facs = (acpi_facs_t *)(uintptr_t)fadt->firmware_ctrl; + facs = (acpi_facs_t *)(uintptr_t)((uint64_t)fadt->x_firmware_ctl_l + | (uint64_t)fadt->x_firmware_ctl_h << 32); if (facs == NULL) { printk(BIOS_ALERT, -- To view, visit https://review.coreboot.org/c/coreboot/+/76293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32 Gerrit-Change-Number: 76293 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi.c: Swap XSDT and RSDT for adding/finding tables
by Lean Sheng Tan (Code Review) 03 Aug '23

03 Aug '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76000?usp=email ) Change subject: acpi.c: Swap XSDT and RSDT for adding/finding tables ...................................................................... acpi.c: Swap XSDT and RSDT for adding/finding tables If ACPI is above 4G it's not possible to have a valid RSDT pointer in RSDP, therefore swap RSDT and XSDT. Both are always generated on x86. On other architectures RSDT is often skipped, e.g. aarch64. On top of that the OS looks at XSDT first. So unconditionally using XSDT and not RSDT is fine. This also deal with the ACPI pointer being above 4G. This currently never happens with x86 platforms. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/acpi/acpi.c 1 file changed, 34 insertions(+), 34 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a2e9fdb..07ca408 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -49,18 +49,15 @@ acpi_rsdt_t *rsdt; acpi_xsdt_t *xsdt = NULL; - /* The RSDT is mandatory... */ + /* The 32bit RSDT may not be valid if tables live above 4GiB */ rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; - - /* ...while the XSDT is not. */ - if (rsdp->xsdt_address) - xsdt = (acpi_xsdt_t *)((uintptr_t)rsdp->xsdt_address); + xsdt = (acpi_xsdt_t *)(uintptr_t)rsdp->xsdt_address; /* This should always be MAX_ACPI_TABLES. */ - entries_num = ARRAY_SIZE(rsdt->entry); + entries_num = ARRAY_SIZE(xsdt->entry); for (i = 0; i < entries_num; i++) { - if (rsdt->entry[i] == 0) + if (xsdt->entry[i] == 0) break; } @@ -70,36 +67,34 @@ return; } - /* Add table to the RSDT. */ - rsdt->entry[i] = (uintptr_t)table; + /* Add table to the XSDT. */ + xsdt->entry[i] = (u64)(uintptr_t)table; - /* Fix RSDT length or the kernel will assume invalid entries. */ - rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1)); + /* Fix XSDT length or the kernel will assume invalid entries. */ + xsdt->header.length = sizeof(acpi_header_t) + (sizeof(u64) * (i + 1)); /* Re-calculate checksum. */ - rsdt->header.checksum = 0; /* Hope this won't get optimized away */ - rsdt->header.checksum = acpi_checksum((u8 *)rsdt, rsdt->header.length); + xsdt->header.checksum = 0; /* Hope this won't get optimized away */ + xsdt->header.checksum = acpi_checksum((u8 *)xsdt, xsdt->header.length); /* - * And now the same thing for the XSDT. We use the same index as for + * And now the same thing for the RSDT. We use the same index as for * now we want the XSDT and RSDT to always be in sync in coreboot. */ - if (xsdt) { - /* Add table to the XSDT. */ - xsdt->entry[i] = (u64)(uintptr_t)table; + if (rsdt && (uintptr_t)table < UINT32_MAX) { + /* Add table to the RSDT. */ + rsdt->entry[i] = (u32)(uintptr_t)table; - /* Fix XSDT length. */ - xsdt->header.length = sizeof(acpi_header_t) + - (sizeof(u64) * (i + 1)); + /* Fix RSDT length. */ + rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1)); /* Re-calculate checksum. */ - xsdt->header.checksum = 0; - xsdt->header.checksum = acpi_checksum((u8 *)xsdt, - xsdt->header.length); + rsdt->header.checksum = 0; + rsdt->header.checksum = acpi_checksum((u8 *)rsdt, rsdt->header.length); } printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n", - i + 1, entries_num, rsdt->header.length); + i + 1, entries_num, xsdt->header.length); } static enum cb_err acpi_fill_header(acpi_header_t *header, const char name[4], @@ -1451,14 +1446,19 @@ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - /* We need at least an RSDP and an RSDT Table */ + /* We need at least an RSDP, RSDT for ACPI 1.0 compat, otherwise XSDT */ rsdp = (acpi_rsdp_t *)current; coreboot_rsdp = (uintptr_t)rsdp; current += sizeof(acpi_rsdp_t); current = acpi_align_current(current); - rsdt = (acpi_rsdt_t *)current; - current += sizeof(acpi_rsdt_t); - current = acpi_align_current(current); + if (current + sizeof(acpi_rsdt_t) - 1 <= UINT32_MAX) { + rsdt = (acpi_rsdt_t *)current; + current += sizeof(acpi_rsdt_t); + current = acpi_align_current(current); + } else { + printk(BIOS_INFO, "Not adding RSDT because tables reside above 4G."); + } + xsdt = (acpi_xsdt_t *)current; current += sizeof(acpi_xsdt_t); current = acpi_align_current(current); @@ -1554,7 +1554,7 @@ void *acpi_find_wakeup_vector(void) { char *p, *end; - acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; acpi_facs_t *facs; acpi_fadt_t *fadt = NULL; acpi_rsdp_t *rsdp = NULL; @@ -1580,13 +1580,13 @@ } printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); - rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; + xsdt = (acpi_xsdt_t *)(uintptr_t)rsdp->xsdt_address; - end = (char *)rsdt + rsdt->header.length; - printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); + end = (char *)xsdt + xsdt->header.length; + printk(BIOS_DEBUG, "XSDT found at %p ends at %p\n", xsdt, end); - for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { - fadt = (acpi_fadt_t *)(uintptr_t)rsdt->entry[i]; + for (i = 0; ((char *)&xsdt->entry[i]) < end; i++) { + fadt = (acpi_fadt_t *)(uintptr_t)xsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) break; fadt = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/76000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Gerrit-Change-Number: 76000 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi.c: Swap XSDT and RSDT for adding/finding tables
by Lean Sheng Tan (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Arthur Heymans, Felix Held, Kapil Porwal, Kyösti Mälkki, Lance Zhao, Nico Huber, Subrata Banik, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76000?usp=email ) Change subject: acpi.c: Swap XSDT and RSDT for adding/finding tables ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Gerrit-Change-Number: 76000 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 01:41:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi.c: Swap XSDT and RSDT for adding/finding tables
by Eric Lai (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Arthur Heymans, Felix Held, Kapil Porwal, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Nico Huber, Subrata Banik, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76000?usp=email ) Change subject: acpi.c: Swap XSDT and RSDT for adding/finding tables ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Gerrit-Change-Number: 76000 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 01:32:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA and NISSA by default
by Eric Lai (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Nick Vaccaro, Subrata Banik, Tarun Tuli, Won Chung. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76873?usp=email ) Change subject: mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA and NISSA by default ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Just to clarify, do you mean split the patch into two? […] yes, all the change are quite similar. -- To view, visit https://review.coreboot.org/c/coreboot/+/76873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1 Gerrit-Change-Number: 76873 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benson Leung <bleung(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 01:32:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Won Chung <wonchung(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amd/soc/common: Use relative offset for AMDFW
by Bao Zheng (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72961?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: amd/soc/common: Use relative offset for AMDFW ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: https://review.coreboot.org/c/coreboot/+/72939 This CL can not be submitted before 72939 -- To view, visit https://review.coreboot.org/c/coreboot/+/72961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Gerrit-Change-Number: 72961 Gerrit-PatchSet: 15 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 01:15:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/mtl: Change default for debug consent from 3 to 6
by Kane Chen (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Tarun Tuli. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76880?usp=email ) Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6 ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76880/comment/9ec2fea8_5815dca5 : PS3, Line 9: USB DBC is very helpful for SoC debug. : TraceHub needs to be enabled in coreboot ifdebug consent == 2 or 4. : Debug consent == 6 enables USB DBC without TraceHub enabled. : This patch changes debug consent to 6 in default to provide basic SoC : debug capability. > Please do not wrap a line, just because a sentence ends, or add a blank line between paragraphs. Done https://review.coreboot.org/c/coreboot/+/76880/comment/dffcbc02_3d69db8c : PS3, Line 14: > Please also mention, you update the config description/help text. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Gerrit-Change-Number: 76880 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 00:55:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/mtl: Change default for debug consent from 3 to 6
by Kane Chen (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Kane Chen, Sridhar Siricilla, Tarun Tuli. Hello Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76880?usp=email to look at the new patch set (#4). Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6 ...................................................................... soc/intel/mtl: Change default for debug consent from 3 to 6 USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/76880/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Gerrit-Change-Number: 76880 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: commonlib/fsp_relocate: Fix pe_relocate() return value on success
by Jérémy Compostella (Code Review) 03 Aug '23

03 Aug '23

Jérémy Compostella has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/76891?usp=email ) Change subject: commonlib/fsp_relocate: Fix pe_relocate() return value on success ...................................................................... commonlib/fsp_relocate: Fix pe_relocate() return value on success Similarly to te_relocate(), on success pe_relocate() should return 0. It has never been an issue so far as pe_relocate() return value is not tested. Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/fsp_relocate.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/76891/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/76891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc Gerrit-Change-Number: 76891 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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