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Change subject: soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONS
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
PS3:
> the LegacyIoEn bit is 0 on reset and setting it will enable the decoding of the following legacy IO […]
Done
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Change subject: util/amdfwtool: Support multiple firmware identifier types
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76585/comment/43102203_9ce72953 :
PS6, Line 10: only one kind of identifier
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/76585/comment/58ebeb36_8f40cf40 :
PS6, Line 11: UUID
> Excuse my ignorance, it’s not clear to me why fwid is not unique compared to UUID. […]
It does not say FWID is not unique. It is just that AMD is adopting UUID for some of the binaries and that list of binaries will be growing in the future. It is a gradual shift and not a total shift.
File util/amdfwtool/amdfwtool.h:
https://review.coreboot.org/c/coreboot/+/76585/comment/c5f7b678_78d60efd :
PS6, Line 333: typedef enum _fwid_type {
: FWID_TYPE_FWID = 0,
: FWID_TYPE_UUID,
: } fwid_type_t;
> The naming is a bit confusing to me, why a UUID should not be a FWID. […]
The firmware binary types are identified using 2 different type of identifiers:
1) 2 bytes FWID
2) 16 bytes UUID
UUID is used as an identifier only for certain binaries and not all. That is why both the types of identifiers have to be supported. There are no datasheets or consistent identification scheme to add a supporting comment. Currently this is evolving on per SoC basis and hence is configured in SoC's fw.cfg
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs
......................................................................
soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs
With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on
reset and setting it will enable the decoding of the following legacy IO
ports:
0x20, 0x21, 0xA0, 0xA1 (PIC);
0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer);
0x70, 0x71, 0x72, 0x73 (RTC);
0x92.
Verstage does not use those legacy IO ports. Also newer SoCs like
Phoenix do not support Legacy I/O registers to access Power Management
registers. Hence enable legacy IO only on platforms that support it.
BUG=b::284984667
TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully
with PSP verstage.
Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/76692/4
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Hello Bao Zheng, Felix Held, Martin Roth, Matt DeVillier, Raul Rangel, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: util/amdfwtool: Support multiple firmware identifier types
......................................................................
util/amdfwtool: Support multiple firmware identifier types
Currently this tool generates a hash table to verify signed binaries,
with a 2 byte FWID as the only kind of identifier. Going forward some
binaries are going to adopt 16 byte UUID identifiers and more binaries
will follow in the future SoCs. Hence add support for handling multiple
firmware identifier types. While at this remove the unused fwid from the
PSP FW table.
BUG=b:277292697
TEST=Build BIOS image and boot to OS in Myst & Skyrim.
Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
M util/amdfwtool/signed_psp.c
3 files changed, 32 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76585/7
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Change subject: soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVER
......................................................................
Patch Set 1: Code-Review+2
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Change subject: acpi/Kconfig: Move unused ACPI_EINJ config option to vendorcode
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> Should we move the ACPI_EINJ code in acpi. […]
Keep forgetting to uncheck resolved...
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Change subject: mb/google/brya/var/agah: Add new GFX devices (igpu) with custom _PLD
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76874/comment/d96fffac_56ebedf9 :
PS1, Line 7: mb/google/brya/var/agah: Add new GFX devices with custom _PLD
> Mention, that it’s an integrated graphics device?
Done
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Change subject: acpi/Kconfig: Move unused ACPI_EINJ config option to vendorcode
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Should we move the ACPI_EINJ code in acpi.[ch] to vendorcode/ocp as well and then add that file to the build when this option is enabled?
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