coreboot-gerrit August 2023

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Generate new TME key on each warm boot
by 9elements QA (Code Review) 04 Aug '23

04 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75627?usp=email ) Change subject: soc/intel/meteorlake: Generate new TME key on each warm boot ...................................................................... Patch Set 13: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 9 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176604 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176602 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176601 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176600 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176599 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176598 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176597 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176596 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176594 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/176593 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176592 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176591 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176590 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176589 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176588 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Gerrit-Change-Number: 75627 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 05:51:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPT...
by Elyes Haouas (Code Review) 04 Aug '23

04 Aug '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76939?usp=email ) Change subject: soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPTIONS ...................................................................... soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPTIONS Move specific selections to {cpx,skx,spr} and remove dummy SOC_SPECIFIC_OPTIONS Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 4 files changed, 31 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/76939/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 24f749a..63ced01 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -4,38 +4,6 @@ config XEON_SP_COMMON_BASE bool - -config SOC_INTEL_SKYLAKE_SP - bool - select XEON_SP_COMMON_BASE - select PLATFORM_USES_FSP2_0 - select NO_FSP_TEMP_RAM_EXIT - help - Intel Skylake-SP support - -config SOC_INTEL_COOPERLAKE_SP - bool - select XEON_SP_COMMON_BASE - select PLATFORM_USES_FSP2_2 - select CACHE_MRC_SETTINGS - select NO_FSP_TEMP_RAM_EXIT - help - Intel Cooper Lake-SP support - -config SOC_INTEL_SAPPHIRERAPIDS_SP - bool - select CACHE_MRC_SETTINGS - select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select PLATFORM_USES_FSP2_3 - select SOC_INTEL_CSE_SERVER_SKU - select XEON_SP_COMMON_BASE - help - Intel Sapphire Rapids-SP support - -if XEON_SP_COMMON_BASE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -72,6 +40,8 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +if XEON_SP_COMMON_BASE + config MAINBOARD_USES_FSP2_0 bool default y diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index aa344ce..f54f771 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -1,10 +1,16 @@ ## SPDX-License-Identifier: GPL-2.0-only -if SOC_INTEL_COOPERLAKE_SP - -config SOC_SPECIFIC_OPTIONS - def_bool y +config SOC_INTEL_COOPERLAKE_SP + bool + select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_2 + select CACHE_MRC_SETTINGS + select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO + help + Intel Cooper Lake-SP support + +if SOC_INTEL_COOPERLAKE_SP config FSP_HEADER_PATH default "3rdparty/fsp/CedarIslandFspBinPkg/Include" diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 18e5f2f5..c2c3d4e 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -1,5 +1,13 @@ ## SPDX-License-Identifier: GPL-2.0-only +config SOC_INTEL_SKYLAKE_SP + bool + select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_0 + select NO_FSP_TEMP_RAM_EXIT + help + Intel Skylake-SP support + if SOC_INTEL_SKYLAKE_SP config MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index c3710ac..9c19f3b 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -1,14 +1,21 @@ ## SPDX-License-Identifier: GPL-2.0-only -if SOC_INTEL_SAPPHIRERAPIDS_SP - -config SOC_SPECIFIC_OPTIONS - def_bool y +config SOC_INTEL_SAPPHIRERAPIDS_SP + bool select MICROCODE_BLOB_NOT_HOOKED_UP select SAVE_MRC_AFTER_FSPS select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select DISABLE_ACPI_HIBERNATE select DEFAULT_X2APIC_RUNTIME + select CACHE_MRC_SETTINGS + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + select PLATFORM_USES_FSP2_3 + select SOC_INTEL_CSE_SERVER_SKU + select XEON_SP_COMMON_BASE + help + Intel Sapphire Rapids-SP support + +if SOC_INTEL_SAPPHIRERAPIDS_SP config CHIPSET_DEVICETREE string -- To view, visit https://review.coreboot.org/c/coreboot/+/76939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0 Gerrit-Change-Number: 76939 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc: Remove SOC_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Jakub Czapiga, Jeff Daly, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Sean Rhodes, Subrata Banik, Tarun Tuli, Tim Chu, Vanessa Eusebio, Werner Zeh. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76487?usp=email ) Change subject: soc: Remove SOC_SPECIFIC_OPTIONS ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/spr/Kconfig: https://review.coreboot.org/c/coreboot/+/76487/comment/3bb3cf84_a923656e : PS2, Line 3: config SOC_INTEL_SAPPHIRERAPIDS_SP > You are overriding the option from soc/intel/xeon_sp/Kconfig here. Same for cpx. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Gerrit-Change-Number: 76487 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 05:28:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc: Remove SOC_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Jakub Czapiga, Jeff Daly, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Sean Rhodes, Subrata Banik, Tarun Tuli, Tim Chu, Vanessa Eusebio, Werner Zeh. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76487?usp=email ) Change subject: soc: Remove SOC_SPECIFIC_OPTIONS ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76487/comment/9bac5971_5c458309 : PS2, Line 8: > nit: Please add more context, just for the record. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Gerrit-Change-Number: 76487 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 05:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCL
by 9elements QA (Code Review) 04 Aug '23

04 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76542?usp=email ) Change subject: mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCL ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 10 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176587 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176585 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176584 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176583 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176582 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176581 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176580 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176579 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/176578 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176577 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/176576 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176575 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176574 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176573 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176572 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176571 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488 Gerrit-Change-Number: 76542 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 04 Aug 2023 04:54:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
by Sridhar Siricilla (Code Review) 04 Aug '23

04 Aug '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76918?usp=email ) Change subject: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails ...................................................................... soc/intel/common: Return CB_ERR when cse_data_clear_request() fails cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index d3fcec7..6203baa 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -751,7 +751,7 @@ if ((status == CSE_UPDATE_DOWNGRADE) || (status == CSE_UPDATE_CORRUPTED)) { if (cse_data_clear_request(cse_bp_info) != CB_SUCCESS) { printk(BIOS_ERR, "cse_lite: CSE data clear failed!\n"); - return CB_SUCCESS; + return CB_ERR; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/76918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Gerrit-Change-Number: 76918 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Subrata Banik (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76921?usp=email ) Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76921/comment/29139f9c_bec126ea : PS3, Line 18: It also adds a : new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with : older generation FSP. > > UPDs are different between just passing BMP image to FSP vs GOP BLT to FSP. > > Can this be better modeled? Subjected to the Intel's FSP design which I haven't seen changed in last several generations before introducing the BMP to BLT buffer change request in Alder Lake. Hence, in short, we don't have any control over it. > > > Are you saying pass the GOP BLT by default (if BMP_LOGO is enabled)? > > Almost. I mean, always built in the driver, but still run-time detect if BMP or BLT should be passed. I guess that could have been done but the problem is we would be ended up compiling extra code "fsp_gop_blt.c" even for older platform where just passing the BMP is enough to get the splash screen. I have added the newer Kconfig to ensure older devices are not getting impacted with this new req of passing BLT buffer instead BMP directly. I hope it clarifies why we need to maintain two different Kconfig option. The UPDs required to pass BLT buffer is not available on the older platform FSP hence, there wouldn’t be any value of calling that extra code. File src/drivers/intel/fsp2_0/fsp_gop_blt.c: PS3: > I meant just a lot of the helper functions introduced here. To make the code readable better. (thats the motivation i had with helper functions) > > Also, will “AMD FSP” ever use this? AMD is using drivers/intel/fsp2_0 anyway hence, they should be able to use it if still using FSP. But as I said, this is SoC dependent code and not sure how cross-arch team will leverage that. -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 04:41:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Generate new TME key on each warm boot
by Subrata Banik (Code Review) 04 Aug '23

04 Aug '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75627?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Generate new TME key on each warm boot ...................................................................... soc/intel/meteorlake: Generate new TME key on each warm boot Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 2eb1405..3fa1347 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -89,6 +89,7 @@ select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + select TME_KEY_REGENERATION_ON_WARM_BOOT select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING -- To view, visit https://review.coreboot.org/c/coreboot/+/75627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Gerrit-Change-Number: 75627 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: src: Implement framework for PRERAM VSD store
by Subrata Banik (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Julius Werner, Kapil Porwal, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76393?usp=email ) Change subject: src: Implement framework for PRERAM VSD store ...................................................................... Patch Set 13: (1 comment) Patchset: PS10: > > If it just one file where we are declaring all required global variables and then migrate into the cbmem, I would have easily follow your instructions but the usage model is different and there would be multiple file and files between the stages are involved hence, write function to sync those global variables after CBMEM comes online is a job honestly. Compared to that, calling into cbmem_vsd is much simpler where the caller adds the newer variable into the VSD and it's getting auto synced when cbmem comes online. > > I really don't follow you here. Where are these multiple files that need to be involved here? Are you talking about code that is not uploaded as part of this patch series yet? Yes. Intel team is working on a new feature implementation which might need to store additional VSD data to be able to access between pre-DRAM init stage and post-ram phase. > As far as I can tell, CB:76395 is the only user of this API, and in that patch the entire code to handle this would be kept within cse_lite.c (and amount to literally one line to declare the variable, one line to memcpy() into it, and a trivial CBMEM_CREATION_HOOK() function to copy it from there into CBMEM). I guess, I'm trying to convey you that, just don't go by *one* variable at this moment. Based on the visibility I have on the in-pipe implementation, there would be atleast 4 such variable which we need to sync between pre-dram and post-dram phase. > All the other stuff from that patch (in ish.c and cse.c) runs in ramstage and would only need to call cbmem_find(). Correct, you might have noticed that I passed the same feedback in the code that cbmem_find() is enough for ramstage stage functions (as sync already initiated) > Or am I misunderstanding something? (Also note that there is plenty of existing precedent for this kind of thing in coreboot already, for example the `mem_chip_info` variable in `src/soc/qualcomm/common/qclib.c`.) > > Meanwhile, I think what you're trying to add here is "messy". You're adding something that sounds like a multi-purpose container ("vendor data"), but really there's only space for a single allocation inside it, and there's no way to identify what kind of data it contains other than reading through the code to find out what was put in there on the other side. Why you think so? reading the VSD data structure will be enough to understand the length and width of this feature (which I can only assume from here it will grow). > What's the point in calling it "vendor data" in the first place, instead of "ISH version", when that's the only thing it can ever really be used for? As mention earlier, CSE version, ISH version, CSE downgrade region, CSE downgrade is initiated or not, such information are expected to be stored into the VSD. We can't land all changes at once. Because there are team working on those feature. And I need to make sure we have base CL ready for them to land the additional changes. > You're making it sound reusable but the way you're writing it it really isn't. Wondering how you can say so? I have visibility on things at Intel side about how things will shape in coming month hence, its easy for me to design things in that way. What you need is to have patients and trust on the implementation that we are not here to make the coreboot messy and don't break other platforms. > And why are you allocating a separate CAR area for something that isn't actually getting passed between stages? We don't want to have multiple static/global variables floating between pre-DRAM and post-DRAM phase hence, the better way to manage things if we relying on the CAR data which would be migrated once we have physical memory. One big data structure to keep required information rather being scattered (like multiple global/static variables). > > I'm sorry, but I just think this is a bad design. It is confusingly named for what it does, it is a lot more complex than it needs to be to solve this problem, and it can't be reused for anything else to justify that extra complexity because now it is already "full" with the ISH version. The size is a kconfig override hence, not big deal to increase the size from soc/mainboard to keep more req information, This is what we do for any pre-ram car variable usage. Don't see anything that different in this implementation. > If you want something that can really be reused for other pre-RAM passing-between-stage needs, then it needs to be able to handle multiple different allocations side by side, and that would essentially be the pre-RAM CBMEM thing that we already agreed was a good idea but takes too long for your time frame right now. Sure, pre-ram cbmem implementations would have been ideal but we don't have that much time in hand (we missed the timeline of 07/31 already) to pick a new implementation and testing (which might take few quarters) to land and enable this feature. -- To view, visit https://review.coreboot.org/c/coreboot/+/76393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0baebb902807d5403800ac18757512bd2a59d2b9 Gerrit-Change-Number: 76393 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 04:32:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Generate new TME key on each warm boot
by Pratikkumar V Prajapati (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ravishankar Sarawadi, Sridhar Siricilla, Subrata Banik, Tarun Tuli. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75627?usp=email ) Change subject: soc/intel/meteorlake: Generate new TME key on each warm boot ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > > Since we are aligned on rest of the patches, i will request our validation team to test one more t […] All tests are passing. removed WIP. -- To view, visit https://review.coreboot.org/c/coreboot/+/75627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Gerrit-Change-Number: 75627 Gerrit-PatchSet: 11 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 04:22:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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