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Change subject: mb/google/rex: Create karis4es variant
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76761/comment/9459c6ee_52197a57 :
PS2, Line 15: WIP, Not tested yet
> Need more information. […]
Jenkins succeeded and it builds all available boards, so it should be fine.
@Eran can you try commands below just to be sure?
```
make crosgcc-i386 -j $(nproc)
util/abuild/abuild -p none -t google/rex -b karis4es -x -a
util/abuild/abuild -p none -t google/rex -b karis -x -a
```
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Change subject: mb/google/rex: Create karis4es variant
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76761/comment/49599720_46a0cab3 :
PS2, Line 15: WIP, Not tested yet
> Need more information.
> Is it built successfully?
@Eran, can you please address this cmt?
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Change subject: mb/google/rex: Create karis4es variant
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Change subject: mb/google/brask/var/kuldax: Set power limit values for RPL SKUs
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76769/comment/3ea3eed5_f65c1986 :
PS3, Line 10: suggestion
Are these values based on any document ? If yes, please add document reference number/ID here.
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Hello Felix Singer, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76830?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/alderlake/chip.h: Use boolean type where applicable
......................................................................
soc/intel/alderlake/chip.h: Use boolean type where applicable
Change-Id: If26184058536590b70bbb03209913118307ff6c5
Signed-off-by: Michael Strosche <michael.strosche(a)gmail.com>
---
M src/soc/intel/alderlake/chip.h
1 file changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/76830/3
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76274?usp=email )
Change subject: nb/intel/sandybridge: Rework nb resource reading
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76274/comment/ffa2fa7b_0c3269f1 :
PS4, Line 10: UMA
Which function are you referring to? Note that "UMA" in the code refers to the ME stolen memory range just below TOM
File src/northbridge/intel/sandybridge/northbridge.c:
https://review.coreboot.org/c/coreboot/+/76274/comment/f36402c7_5da8ab7a :
PS2, Line 151: mmio_from_to(dev, index++, me_base, tom);
> This seems weird and potentially crossing 4GiB boundary?
ME UMA is placed just below TOM (Top Of Memory), and TOM is the total installed DRAM capacity. ME UMA is 32 MiB or 64 MiB (can't remember), DIMM sizes are powers of 2 and this platform supports up to 4 DIMMs: no combination of DIMMs can result in ME UMA crossing the 4 GiB boundary.
Then again, the code is quite confusing.
File src/northbridge/intel/sandybridge/northbridge.c:
https://review.coreboot.org/c/coreboot/+/76274/comment/395ef625_e0a758de :
PS3, Line 161: printk(BIOS_DEBUG, "DPR base 0x%08lx size %luM\n", dpr_base, dpr_size / MiB);
> clang throws this, gcc does not: […]
`uintptr_t` is supposed to be printed using the `PRIxPTR` macro. For `size_t`, the correct way to print is with `%zu` (or `%zx` for hex).
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