coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Add power limits for N4500/N5100
by Eric Lai (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Paul Menzel, Stanley Wu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76876?usp=email ) Change subject: mb/google/dedede/var/boxy: Add power limits for N4500/N5100 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Gerrit-Change-Number: 76876 Gerrit-PatchSet: 3 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 03:38:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu: Get rid of CPU_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 04 Aug '23

04 Aug '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76681?usp=email ) Change subject: cpu: Get rid of CPU_SPECIFIC_OPTIONS ...................................................................... cpu: Get rid of CPU_SPECIFIC_OPTIONS Remove dummy CPU_SPECIFIC_OPTIONS. Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_p/Kconfig 11 files changed, 21 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 5b4f6fc..5bcdd98 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -1,11 +1,6 @@ config CPU_INTEL_HASWELL bool - -if CPU_INTEL_HASWELL - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select SSE2 select UDELAY_TSC @@ -19,6 +14,8 @@ select HAVE_ASAN_IN_ROMSTAGE select CPU_INTEL_COMMON_VOLTAGE +if CPU_INTEL_HASWELL + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index bced054..a8d445c 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_2065X bool - -if CPU_INTEL_MODEL_2065X - -config CPU_SPECIFIC_OPTIONS - def_bool y select HAVE_EXP_X86_64_SUPPORT select ARCH_X86 select SSE2 @@ -16,6 +11,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_MODEL_2065X + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 479dbbb..10c0ae3 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_206AX bool - -if CPU_INTEL_MODEL_206AX - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT select SSE2 @@ -16,6 +11,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_MODEL_206AX + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index c30e066..4ba8747 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -2,11 +2,6 @@ config CPU_INTEL_SLOT_1 bool - -if CPU_INTEL_SLOT_1 - -config SLOT_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X select CPU_INTEL_MODEL_68X @@ -19,6 +14,8 @@ select SETUP_XIP_CACHE select RESERVE_MTRRS_FOR_OS +if CPU_INTEL_SLOT_1 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index ca6990d..1a549ac 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -1,13 +1,10 @@ config CPU_INTEL_SOCKET_441 bool - -if CPU_INTEL_SOCKET_441 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_106CX select SETUP_XIP_CACHE +if CPU_INTEL_SOCKET_441 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 84bb06d..b56fb88 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,12 +1,9 @@ config CPU_INTEL_SOCKET_BGA956 bool + select CPU_INTEL_MODEL_1067X if CPU_INTEL_SOCKET_BGA956 -config SOCKET_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_MODEL_1067X - config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 9f1fbbb..223f80d 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,15 +1,12 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + select CPU_INTEL_MODEL_106CX + select CPU_HAS_L2_ENABLE_MSR help Select this socket on Intel Pineview if CPU_INTEL_SOCKET_FCBGA559 -config SOCKET_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_MODEL_106CX - select CPU_HAS_L2_ENABLE_MSR - config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 897b032..63d6250 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -1,16 +1,13 @@ config CPU_INTEL_SOCKET_LGA775 bool - -if CPU_INTEL_SOCKET_LGA775 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X select CPU_INTEL_MODEL_1067X select SIPI_VECTOR_IN_ROM +if CPU_INTEL_SOCKET_LGA775 + config DCACHE_RAM_SIZE hex default 0x8000 # 32 kB diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 6285e82..2e653e9 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -1,13 +1,10 @@ config CPU_INTEL_SOCKET_M bool - -if CPU_INTEL_SOCKET_M - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX +if CPU_INTEL_SOCKET_M + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index dcf0e98..8f28670 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_SOCKET_MPGA604 bool - -if CPU_INTEL_SOCKET_MPGA604 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_F2X select UDELAY_TSC select TSC_MONOTONIC_TIMER @@ -12,6 +7,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_SOCKET_MPGA604 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 12e078c..90bfdc9 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -1,13 +1,10 @@ config CPU_INTEL_SOCKET_P bool - -if CPU_INTEL_SOCKET_P - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX +if CPU_INTEL_SOCKET_P + config DCACHE_RAM_BASE hex default 0xfefc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/76681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e Gerrit-Change-Number: 76681 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECT
by Reka Norman (Code Review) 04 Aug '23

04 Aug '23

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76938?usp=email ) Change subject: mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECT ...................................................................... mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECT BUG=b:279097356 TEST=On dibbi: - flash OS 15449.0.0 (where suspend is broken due to b:274531972) - run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28` - check the AP wakes up immediately when the EC detects a sleep hang Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/76938/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index 6b5b0d0..1e4ac0b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -51,7 +51,8 @@ #define MAINBOARD_EC_S0IX_WAKE_EVENTS \ (MAINBOARD_EC_S3_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ -- To view, visit https://review.coreboot.org/c/coreboot/+/76938?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55 Gerrit-Change-Number: 76938 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add DPTF parameters
by Van Chen (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Derek Huang, Ian Feng, Rex Chou, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli. Van Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76712?usp=email ) Change subject: mb/google/nissa/var/craaskov: Add DPTF parameters ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > Please also mention TCC change in comment. done. mb/google/nissa/var/craaskov: Add DPTF parameters The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" -- To view, visit https://review.coreboot.org/c/coreboot/+/76712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Gerrit-Change-Number: 76712 Gerrit-PatchSet: 8 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:53:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add DPTF parameters
by Van Chen (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Derek Huang, Ian Feng, Rex Chou, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Van Chen. Hello Derek Huang, Dtrain Hsu, Eric Lai, Ian Feng, John Su, Rex Chou, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76712?usp=email to look at the new patch set (#8). Change subject: mb/google/nissa/var/craaskov: Add DPTF parameters ...................................................................... mb/google/nissa/var/craaskov: Add DPTF parameters The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" BUG=b:290705146 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Signed-off-by: Van Chen <van_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/76712/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Gerrit-Change-Number: 76712 Gerrit-PatchSet: 8 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add DPTF parameters
by Eric Lai (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Derek Huang, Ian Feng, Rex Chou, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Van Chen. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76712?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/craaskov: Add DPTF parameters ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: Please also mention TCC change in comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/76712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Gerrit-Change-Number: 76712 Gerrit-PatchSet: 7 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:47:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add DPTF parameters
by Dtrain Hsu (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Derek Huang, Eric Lai, Ian Feng, Rex Chou, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Van Chen. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76712?usp=email ) Change subject: mb/google/nissa/var/craaskov: Add DPTF parameters ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Gerrit-Change-Number: 76712 Gerrit-PatchSet: 7 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:45:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Add power limits for N4500/N5100
by Stanley Wu (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Paul Menzel, Subrata Banik. Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76876?usp=email ) Change subject: mb/google/dedede/var/boxy: Add power limits for N4500/N5100 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76876/comment/5fd89a6f_924f0243 : PS1, Line 12: TEST=emerge-dedede coreboot and read correct value on boxy > Maybe paste those into the “test section” of the git commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Gerrit-Change-Number: 76876 Gerrit-PatchSet: 3 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:41:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src: Store CSE RW FW version during cse_fw_sync
by Dinesh Gehlot (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal, Subrata Banik. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76395?usp=email ) Change subject: src: Store CSE RW FW version during cse_fw_sync ...................................................................... Patch Set 10: (4 comments) File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/76395/comment/00f882d1_fb4d1fa5 : PS9, Line 90: #define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056 > drop this is a separate CL Acknowledged File src/drivers/intel/ish/ish.c: https://review.coreboot.org/c/coreboot/+/76395/comment/0374f24f_c9095074 : PS9, Line 53: cbmem_vsd_find() > why can't i still use `cbmem_find(CBMEM_ID_VSD)` Acknowledged File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/76395/comment/3be10867_77ccf004 : PS9, Line 1424: cbmem_vsd_find > same Acknowledged File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/76395/comment/24e2e127_39e121ef : PS9, Line 1267: cbmem_vsd_find > same Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/76395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95ce7e1584aae6be3c431f07f8d8e5001e7854a Gerrit-Change-Number: 76395 Gerrit-PatchSet: 10 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src: Implement framework for PRERAM VSD store
by Dinesh Gehlot (Code Review) 04 Aug '23

04 Aug '23

Attention is currently required from: Arthur Heymans, Kapil Porwal, Lean Sheng Tan, Subrata Banik, Werner Zeh. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76393?usp=email ) Change subject: src: Implement framework for PRERAM VSD store ...................................................................... Patch Set 13: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76393/comment/f82be437_59405a16 : PS10, Line 7: src/ > Please remove. Acknowledged https://review.coreboot.org/c/coreboot/+/76393/comment/6286cecc_b4d922da : PS10, Line 8: > Please describe the problem, you are trying to solve. Updated description. Commit Message: https://review.coreboot.org/c/coreboot/+/76393/comment/809e3fdb_27ad0921 : PS12, Line 9: This patch implements a framework that stores Vendor Specific Data > > `'intialized' may be misspelled - perhaps 'initialized'?` […] Acknowledged File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/76393/comment/3728e8fd_0943f3de : PS12, Line 91: 0x43565344 > signature should be `_VSD` in little-endian format Acknowledged File src/cpu/intel/car/romstage.c: https://review.coreboot.org/c/coreboot/+/76393/comment/23d308be_604c12e4 : PS12, Line 9: #include <cbmem_vsd.h> > Remove it. Acknowledged File src/lib/cbmem_vsd.c: https://review.coreboot.org/c/coreboot/+/76393/comment/928d9ce4_0c9258f6 : PS12, Line 40: : user_area = cbmem_add(CBMEM_ID_VSD, req_size); : > brace around Acknowledged https://review.coreboot.org/c/coreboot/+/76393/comment/47e3fb56_09ee4d03 : PS12, Line 55: if(!cbmem_area) > > `space required before the open parenthesis '('` […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/76393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0baebb902807d5403800ac18757512bd2a59d2b9 Gerrit-Change-Number: 76393 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 04 Aug 2023 02:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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