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Change in coreboot[master]: ec: Add support for MEC5055 for Dell laptops
by Iru Cai (vimacs) (Code Review) 18 Sep '23

18 Sep '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44975 to review the following change. Change subject: ec: Add support for MEC5055 for Dell laptops ...................................................................... ec: Add support for MEC5055 for Dell laptops This EC support code is required to boot various Dell Latitude laptops, otherwise the laptop will shut down in a minute after powered on. Tested on Dell Latitude E7240. Change-Id: Iee68ea52dcf0242315868a46b5e4768303e30dce Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/ec/dell/mec5055/Kconfig A src/ec/dell/mec5055/Makefile.inc A src/ec/dell/mec5055/early_init.c A src/ec/dell/mec5055/mec5055.c A src/ec/dell/mec5055/mec5055.h 5 files changed, 148 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44975/1 diff --git a/src/ec/dell/mec5055/Kconfig b/src/ec/dell/mec5055/Kconfig new file mode 100644 index 0000000..a7bf9a5 --- /dev/null +++ b/src/ec/dell/mec5055/Kconfig @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_DELL_MEC5055 + bool diff --git a/src/ec/dell/mec5055/Makefile.inc b/src/ec/dell/mec5055/Makefile.inc new file mode 100644 index 0000000..9cdfbb3 --- /dev/null +++ b/src/ec/dell/mec5055/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_EC_DELL_MEC5055),y) + +bootblock-y += mec5055.c early_init.c +romstage-y += mec5055.c early_init.c + +endif diff --git a/src/ec/dell/mec5055/early_init.c b/src/ec/dell/mec5055/early_init.c new file mode 100644 index 0000000..6aec48b --- /dev/null +++ b/src/ec/dell/mec5055/early_init.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "mec5055.h" + +void mec5055_early_init(void) +{ + u8 buf[32], c; + + mec5055_ec_command_0(buf, 0xc2, 0); + mec5055_ec_command_1(0xab, NULL, 0, &c, 1); +} diff --git a/src/ec/dell/mec5055/mec5055.c b/src/ec/dell/mec5055/mec5055.c new file mode 100644 index 0000000..2deec7d --- /dev/null +++ b/src/ec/dell/mec5055/mec5055.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/io.h> +#include "mec5055.h" + +static const u16 EC_CTRL = 0x910; +static const u16 EC_DATA = 0x911; + +static void wait_ec(void) +{ + u8 v; + do { + outb(0, EC_CTRL); + v = inb(EC_DATA); + } while (v != 0); +} + +static int read_ec_regs(u8 start, u8 *sdata, u8 count) +{ + if (start >= 0x20 || start + count > 0x20) + return -1; + + if (count <= 0) + return 0; + + while (count--) { + outb(start + 0x10, EC_CTRL); + *sdata = inb(EC_DATA); + sdata++; + start++; + } + + return 0; +} + +static int write_ec_regs(u8 start, const u8 *sdata, u8 count) +{ + if (start >= 0x20 || start + count > 0x20) + return -1; + + if (count <= 0) + return 0; + + while (count--) { + outb(start + 0x10, EC_CTRL); + outb(*sdata, EC_DATA); + sdata++; + start++; + } + + return 0; +} + +/* Steps to communicate with the EC: + * 1. send command: + * - write arguments to EC[2:] + * - send 0 to CTRL then cmd to DATA + * 2. wait EC + * 3. receive result: result may starts at EC[0] or EC[1] + */ + +/* send command to EC and wait, command at cmd[0], args in cmd[2:] */ +static int ec_send_command(const u8 *cmd, int argc) +{ + int result = 0; + + if (argc > 0) { + if (argc > 0x1e) + result = -1; + else + result = write_ec_regs(2, cmd + 2, argc); + } + + outb(0, EC_CTRL); + outb(cmd[0], EC_DATA); + wait_ec(); + return result; +} + +/* receive result from EC[0:] */ +int mec5055_ec_command_0(u8 *buf, u8 cmd, int argc) +{ + buf[0] = cmd; + int res = ec_send_command(buf, argc); + if (res < 0) + return res; + + return read_ec_regs(0, buf, 0x10); +} + +/* receive result from EC[1:] */ +int mec5055_ec_command_1(u8 cmd, const u8 *cmd_buf, int argc, u8 *res_buf, int res_size) +{ + if (argc >= 0x1e) + argc = 0x1e; + + if (res_size >= 0x1f) + res_size = 0x1f; + + int t = write_ec_regs(2, cmd_buf, argc); + if (t < 0) + return t; + + outb(0, EC_CTRL); + outb(cmd, EC_DATA); + wait_ec(); + + return read_ec_regs(1, res_buf, res_size); +} diff --git a/src/ec/dell/mec5055/mec5055.h b/src/ec/dell/mec5055/mec5055.h new file mode 100644 index 0000000..33c6a1d --- /dev/null +++ b/src/ec/dell/mec5055/mec5055.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _EC_DELL_MEC5055_H_ +#define _EC_DELL_MEC5055_H_ + +#include <stddef.h> +#include <stdint.h> + +int mec5055_ec_command_0(u8 *buf, u8 cmd, int argc); +int mec5055_ec_command_1(u8 cmd, const u8 *cmd_buf, int argc, u8 *res_buf, int res_size); +void mec5055_early_init(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee68ea52dcf0242315868a46b5e4768303e30dce Gerrit-Change-Number: 44975 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 10

Change in coreboot[master]: mainboard/dell: Add Latitude E7440
by Pablo Stebler (Code Review) 18 Sep '23

18 Sep '23

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46540 ) Change subject: mainboard/dell: Add Latitude E7440 ...................................................................... mainboard/dell: Add Latitude E7440 Based on autoport output. Untested for now. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e --- M src/mainboard/dell/latitude_e7x40/Kconfig M src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb 6 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46540/1 diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig index 05ed643..9b9bae7 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -23,10 +23,12 @@ config VARIANT_DIR string default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 + default "latitude_e7440" if BOARD_DELL_LATITUDE_E7440 config MAINBOARD_PART_NUMBER string default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 + default "Latitude E7440" if BOARD_DELL_LATITUDE_E7440 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name index 5eefdf7..4532758 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig.name +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -4,3 +4,8 @@ bool "Latitude E7240" select BOARD_DELL_LATITUDE_E7x40 + +config BOARD_DELL_LATITUDE_E7440 + bool "Latitude E7440" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt new file mode 100644 index 0000000..6d6a545 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c new file mode 100644 index 0000000..89531a3 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c new file mode 100644 index 0000000..e358006 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805cb, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805cb), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb new file mode 100644 index 0000000..cc31dc8 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05cb inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e Gerrit-Change-Number: 46540 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [DO NOT MERGE] q1900m
by Angel Pons (Code Review) 08 Sep '23

08 Sep '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39658 ) Change subject: [DO NOT MERGE] q1900m ...................................................................... [DO NOT MERGE] q1900m Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/dptf.asl A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/mainboard.c A src/mainboard/asrock/q1900m/romstage.c A src/mainboard/asrock/q1900m/spd/spd0.spd.hex A src/mainboard/asrock/q1900m/spd/spd1.spd.hex 18 files changed, 841 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/1 diff --git a/src/mainboard/asrock/q1900m/Kconfig b/src/mainboard/asrock/q1900m/Kconfig new file mode 100644 index 0000000..79db93c --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_ASROCK_Q1900M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_HAS_CHROMEOS + +config MAINBOARD_DIR + string + default "asrock/q1900m" + +config MAINBOARD_PART_NUMBER + string + default "Q1900M" + +config VGA_BIOS_FILE + string + default "pci8086,0f31.rom" + +endif diff --git a/src/mainboard/asrock/q1900m/Kconfig.name b/src/mainboard/asrock/q1900m/Kconfig.name new file mode 100644 index 0000000..1056ef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_Q1900M + bool "Q1900M" diff --git a/src/mainboard/asrock/q1900m/Makefile.inc b/src/mainboard/asrock/q1900m/Makefile.inc new file mode 100644 index 0000000..8947e78 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Makefile.inc @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = spd0 +SPD_SOURCES += spd1 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd + +ramstage-y += irqroute.c +ramstage-y += gpio.c diff --git a/src/mainboard/asrock/q1900m/acpi/dptf.asl b/src/mainboard/asrock/q1900m/acpi/dptf.asl new file mode 100644 index 0000000..bdc396b --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/dptf.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 80 + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, // Revision + Package () { // Power Limit 1 + 0, // PowerLimitIndex, 0 for Power Limit 1 + 1600, // PowerLimitMinimum + 6200, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 200 // StepSize + }, + Package () { // Power Limit 2 + 1, // PowerLimitIndex, 1 for Power Limit 2 + 8000, // PowerLimitMinimum + 8000, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 1000 // StepSize + } +}) + +/* Include SoC DPTF */ +#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/q1900m/acpi/ec.asl b/src/mainboard/asrock/q1900m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/ec.asl diff --git a/src/mainboard/asrock/q1900m/acpi/superio.asl b/src/mainboard/asrock/q1900m/acpi/superio.asl new file mode 100644 index 0000000..e224349 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/superio.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/q1900m/acpi_tables.c b/src/mainboard/asrock/q1900m/acpi_tables.c new file mode 100644 index 0000000..c8a95c6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi_tables.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/asrock/q1900m/board_info.txt b/src/mainboard/asrock/q1900m/board_info.txt new file mode 100644 index 0000000..d3e1fc2 --- /dev/null +++ b/src/mainboard/asrock/q1900m/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Q1900M/ +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: possible +Flashrom support: y diff --git a/src/mainboard/asrock/q1900m/devicetree.cb b/src/mainboard/asrock/q1900m/devicetree.cb new file mode 100644 index 0000000..3085696 --- /dev/null +++ b/src/mainboard/asrock/q1900m/devicetree.cb @@ -0,0 +1,118 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "1" + register "ide_legacy_combined" = "0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0" + register "usb3_port_disable_mask" = "0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuning for Q1900M board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + #register "gpu_pipea_port_select" = "2" # DP_C + #register "gpu_pipea_power_cycle_delay" = "6" # 600ms + #register "gpu_pipea_power_on_delay" = "5000" # 500ms + #register "gpu_pipea_light_on_delay" = "70" # 7ms + #register "gpu_pipea_power_off_delay" = "500" # 50ms + #register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on # LPC Bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 off # Keyboard + #io 0x60 = 0x60 + #io 0x62 = 0x64 + #irq 0x70 = 1 + #irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-Pull or Open-drain + device pnp 2e.14 off end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/asrock/q1900m/dsdt.asl b/src/mainboard/asrock/q1900m/dsdt.asl new file mode 100644 index 0000000..2e9de53 --- /dev/null +++ b/src/mainboard/asrock/q1900m/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + #include <soc/intel/baytrail/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + + /* Dynamic Platform Thermal Framework */ + //#include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asrock/q1900m/fadt.c b/src/mainboard/asrock/q1900m/fadt.c new file mode 100644 index 0000000..d07d157 --- /dev/null +++ b/src/mainboard/asrock/q1900m/fadt.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <string.h> +#include <soc/acpi.h> +#include <version.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->reserved = 0; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/asrock/q1900m/gpio.c b/src/mainboard/asrock/q1900m/gpio.c new file mode 100644 index 0000000..c1dfef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * Note that Pad Number differs from GPIO Number. The pads list is in the BWG Vol2 Rev1p0. + * Chapter 35: GPIO Handling + * Table 35-2: Pad Number Mapping According to Pad Name + */ + + #define GPIO_INNC GPIO_INPUT_NOPU + #define GPIO_FS GPIO_INPUT_NOPU + +/* DDI0 = HDMI; DDI1 = DVI; no backlight used on either pipe */ + +/* NCORE GPIOs */ /* Map [15..26] to MCSI_GPIO[00..11] */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* [00] - HDMI DDC Detect */ // DDI0_HPD + GPIO_FUNC2, /* [01] - HDMI DDC Data */ // DDI0_DDCDATA + GPIO_FUNC2, /* [02] - HDMI DDC Clock */ // DDI0_DDCCLK + GPIO_INNC, /* [03] - No Connect */ // DDI0_VDDEN + GPIO_INNC, /* [04] - No Connect */ // DDI0_BKLTEN + GPIO_INNC, /* [05] - No Connect */ // DDI0_BKLTCTL + GPIO_FUNC2, /* [06] - DVI DDC Detect */ // DDI1_HPD + GPIO_FUNC2, /* [07] - DVI DDC Data */ // DDI1_DDCDATA + GPIO_FUNC2, /* [08] - DVI DDC Clock */ // DDI1_DDCCLK + GPIO_INNC, /* [09] - No Connect */ // DDI1_VDDEN + GPIO_INNC, /* [10] - No Connect */ // DDI1_BKLTEN + GPIO_INNC, /* [11] - No Connect */ // DDI1_BKLTCTL + GPIO_INNC, /* [12] - No Connect */ // RESERVED + GPIO_FS, /* [13] - No Connect */ // RESERVED (removed in EDS_Rev1p5) + GPIO_INNC, /* [14] - No Connect */ // RESERVED + GPIO_INNC, /* [15] - No Connect */ // OBSFN_C0 (XDP stuff) + GPIO_INNC, /* [16] - No Connect */ // XDP stuff + GPIO_INNC, /* [17] - No Connect */ // XDP stuff + GPIO_INNC, /* [18] - No Connect */ // XDP stuff + GPIO_INNC, /* [19] - No Connect */ // XDP stuff + GPIO_INNC, /* [20] - No Connect */ // XDP stuff + GPIO_INNC, /* [21] - No Connect */ // XDP stuff + GPIO_INNC, /* [22] - No Connect */ // XDP stuff + GPIO_INNC, /* [23] - No Connect */ // XDP stuff + GPIO_INNC, /* [24] - No Connect */ // Still camera 0 reset + GPIO_INNC, /* [25] - No Connect */ // Still camera 1 reset + GPIO_INNC, /* [26] - No Connect */ // Video camera reset + GPIO_END +}; + +/* SCORE GPIOs (_XX) */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FS, /* [000] - SATA_GP0 */ // SHOULD BE A PULL-UP, BUT READS LOW! + GPIO_FS, /* [001] - SATA_GP1 */ // EXTERNAL PULL UP + GPIO_FUNC1, /* [002] - SATA_LED_B */ // HDD LED + GPIO_FUNC1, /* [003] - PCIE_CLKREQ_0 */ // CLKREQ# FOR TOP PCIE X1 + GPIO_FUNC1, /* [004] - PCIE_CLKREQ_1 */ // CLKREQ# FOR PCIE X4 + GPIO_FUNC1, /* [005] - PCIE_CLKREQ_2 */ // CLKREQ# FOR BOTTOM PCIE X1 + GPIO_FUNC1, /* [006] - PCIE_CLKREQ_3 */ // CLKREQ# FOR LAN + GPIO_INNC, /* [007] - SD3_WP */ // NO CONNECT + GPIO_FUNC2, /* [008] - No Connect */ // HDA RESET + GPIO_FUNC2, /* [009] - No Connect */ // HDA SYNC + GPIO_FUNC2, /* [010] - No Connect */ // HDA CLK + GPIO_FUNC2, /* [011] - No Connect */ // HDA SDO + GPIO_FUNC2, /* [012] - No Connect */ // HDA SDI0 + GPIO_INNC, /* [013] - No Connect */ // NO CONNECT + GPIO_FS, /* [014] - No Connect */ // OTE_GATE1 !!! + GPIO_FS, /* [015] - No Connect */ // OTE_GATE2 !!! + GPIO_INNC, /* [016] - No Connect */ // NO CONNECT + GPIO_INNC, /* [017] - No Connect */ // NO CONNECT + GPIO_INNC, /* [018] - No Connect */ // NO CONNECT + GPIO_INNC, /* [019] - No Connect */ // NO CONNECT + GPIO_INNC, /* [020] - No Connect */ // NO CONNECT + GPIO_INNC, /* [021] - No Connect */ // NO CONNECT + GPIO_INNC, /* [022] - No Connect */ // NO CONNECT + GPIO_INNC, /* [023] - No Connect */ // NO CONNECT + GPIO_INNC, /* [024] - No Connect */ // NO CONNECT + GPIO_INNC, /* [025] - No Connect */ // NO CONNECT + GPIO_INNC, /* [026] - No Connect */ // NO CONNECT + GPIO_INNC, /* [027] - No Connect */ // NO CONNECT + GPIO_INNC, /* [028] - No Connect */ // NO CONNECT + GPIO_INNC, /* [029] - No Connect */ // NO CONNECT + GPIO_INNC, /* [030] - No Connect */ // NO CONNECT + GPIO_INNC, /* [031] - No Connect */ // NO CONNECT + GPIO_INNC, /* [032] - No Connect */ // NO CONNECT + GPIO_INNC, /* [033] - SD3_CLK */ // NO CONNECT + GPIO_INNC, /* [034] - SD3_D0 */ // NO CONNECT + GPIO_INNC, /* [035] - SD3_D1 */ // NO CONNECT + GPIO_INNC, /* [036] - SD3_D2 */ // NO CONNECT + GPIO_INNC, /* [037] - SD3_D3 */ // NO CONNECT + GPIO_INNC, /* [038] - SD3_CD# */ // NO CONNECT + GPIO_INNC, /* [039] - SD3_CMD */ // NO CONNECT + GPIO_INNC, /* [040] - No Connect */ // NO CONNECT + GPIO_INNC, /* [041] - SD3_PWREN */ // NO CONNECT + GPIO_FUNC1, /* [042] - No Connect */ // LAD0 + GPIO_FUNC1, /* [043] - No Connect */ // LAD1 + GPIO_FUNC1, /* [044] - No Connect */ // LAD2 + GPIO_FUNC1, /* [045] - No Connect */ // LAD3 + GPIO_FUNC1, /* [046] - No Connect */ // LFRAME# + GPIO_FUNC1, /* [047] - No Connect */ // LPC CLOCK (TPM) + GPIO_FUNC1, /* [048] - No Connect */ // LPC CLOCK (SIO) + GPIO_FUNC1, /* [049] - No Connect */ // LPC CLKRUN# + GPIO_FUNC1, /* [050] - No Connect */ // SERIRQ# + GPIO_FUNC1, /* [051] - PCU_SMB_DATA */ // SMBUS DATA + GPIO_FUNC1, /* [052] - PCU_SMB_CLK */ // SMBUS CLK + GPIO_FUNC1, /* [053] - PCU_SMB_ALERT */ // SMBUS ALERT# (UNUSED? STRAP?) + GPIO_FUNC1, /* [054] - ILB_8254_SPKR */ // SPEAKER + GPIO_FS, /* [055] - No Connect */ // FRONT PANEL PRESENCE (PIN 4) + GPIO_FS, /* [056] - _56 */ // TOP SWAP (DEFEATURE) + GPIO_INNC, /* [057] - PCU_UART3_TXD */ // NO CONNECT + GPIO_INNC, /* [058] - No Connect */ // NO CONNECT + GPIO_INNC, /* [059] - No Connect */ // NO CONNECT + GPIO_INNC, /* [060] - No Connect */ // NO CONNECT + GPIO_FS, /* [061] - PCU_UART3_RXD */ // PCIE3_SEL !!! + GPIO_INNC, /* [062] - LPE_I2S_CLK */ // NO CONNECT + GPIO_FS, /* [063] - LPE_I2S_FRM */ // BOOT SEL STRAP + GPIO_INNC, /* [064] - LPE_I2S_DATIN */ // NO CONNECT + GPIO_FS, /* [065] - LPE_I2S_DATOUT */ // IFD OVERRIDE STRAP + GPIO_INNC, /* [066] - SOC_SIO_SPI_CS1 */ // NO CONNECT + GPIO_INNC, /* [067] - SOC_SIO_SPI_MISO */ // NO CONNECT + GPIO_INNC, /* [068] - SOC_SIO_SPI_MOSI */ // NO CONNECT + GPIO_INNC, /* [069] - SOC_SIO_SPI_CLK */ // NO CONNECT + GPIO_INNC, /* [070] - SIO_UART1_RXD */ // NO CONNECT + GPIO_INNC, /* [071] - SIO_UART1_TXD */ // NO CONNECT + GPIO_INNC, /* [072] - No Connect */ // NO CONNECT + GPIO_INNC, /* [073] - No Connect */ // NO CONNECT + GPIO_INNC, /* [074] - No Connect */ // NO CONNECT + GPIO_INNC, /* [075] - No Connect */ // NO CONNECT + GPIO_INNC, /* [076] - No Connect */ // NO CONNECT + GPIO_INNC, /* [077] - No Connect */ // NO CONNECT + GPIO_INNC, /* [078] - No Connect */ // NO CONNECT + GPIO_INNC, /* [079] - No Connect */ // NO CONNECT + GPIO_INNC, /* [080] - No Connect */ // NO CONNECT + GPIO_INNC, /* [081] - No Connect */ // NO CONNECT + GPIO_INNC, /* [082] - No Connect */ // NO CONNECT + GPIO_INNC, /* [083] - No Connect */ // NO CONNECT + GPIO_INNC, /* [084] - No Connect */ // NO CONNECT + GPIO_INNC, /* [085] - No Connect */ // NO CONNECT + GPIO_INNC, /* [086] - No Connect */ // NO CONNECT + GPIO_INNC, /* [087] - No Connect */ // NO CONNECT + GPIO_INNC, /* [088] - No Connect */ // NO CONNECT + GPIO_INNC, /* [089] - No Connect */ // NO CONNECT + GPIO_INNC, /* [090] - EXP_I2C_SDA */ // NO CONNECT + GPIO_INNC, /* [091] - EXP_I2C_SCL */ // NO CONNECT + GPIO_FS, /* [092] - 0R GND? */ // PCIE1_SEL !!! + GPIO_FS, /* [093] - 0R GND? */ // PCIE2_SEL !!! + GPIO_INNC, /* [094] - SOC_PWM0 */ // NO CONNECT + GPIO_INNC, /* [095] - SOC_PWM1 */ // NO CONNECT + GPIO_FUNC1, /* [096] - No Connect */ // PMC PLT CLK0 + GPIO_FUNC1, /* [097] - No Connect */ // PMC PLT CLK1 + GPIO_INNC, /* [098] - No Connect */ // NO CONNECT + GPIO_INNC, /* [099] - No Connect */ // NO CONNECT + GPIO_INNC, /* [100] - No Connect */ // NO CONNECT + GPIO_INNC, /* [101] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* SSUS GPIOs () */ +static const struct soc_gpio_map gp_ssus_gpio_map[] = { + GPIO_FS, /* [00] - No Connect */ // RINGIN# !!! + GPIO_INNC, /* [01] - PMC_WAKE_PCIE[1] */ // NO CONNECT + GPIO_INNC, /* [02] - PMC_WAKE_PCIE[2] */ // PME# (SIO) + GPIO_INNC, /* [03] - PMC_WAKE_PCIE[3] */ // SMI# (SIO) + GPIO_INNC, /* [04] - No Connect */ // NO CONNECT + GPIO_INNC, /* [05] - No Connect */ // NO CONNECT + GPIO_INNC, /* [06] - No Connect */ // NO CONNECT + GPIO_INNC, /* [07] - No Connect */ // NO CONNECT + GPIO_INNC, /* [08] - No Connect */ // NO CONNECT + GPIO_INNC, /* [09] - No Connect */ // NO CONNECT + GPIO_INNC, /* [10] - _10_UNLOCK */ // NO CONNECT + GPIO_FUNC0, /* [11] - SUSPWRDNACK */ // SUSPWRDNACK + GPIO_FS, /* [12] - No Connect */ // NO CONNECT ??? + GPIO_INNC, /* [13] - No Connect */ // NO CONNECT + GPIO_INNC, /* [14] - 14_J20 */ // NO CONNECT + GPIO_FUNC0, /* [15] - PMC_WAKE_PCIE[0] */ // SOC PCIE WAKE# + GPIO_FUNC0, /* [16] - No Connect */ // POWER BUTTON (SIO) + GPIO_INNC, /* [17] - No Connect */ // NO CONNECT + GPIO_FUNC0, /* [18] - T360 */ // SUS STAT# + GPIO_FUNC0, /* [19] - SOC_USB_HOST_OC0 */ // USB OC0# + GPIO_FUNC0, /* [20] - SOC_USB_HOST_OC1 */ // USB OC1# + GPIO_INNC, /* [21] - SOC_SPI_CS1B */ // NO CONNECT + GPIO_OUT_LOW, /* [22] - No Connect */ // MEMORY VR VCCM OV1 !!! + GPIO_FS, /* [23] - No Connect */ // MEMORY VR VCCM OV2 !!! + GPIO_INNC, /* [24] - No Connect */ // NO CONNECT + GPIO_INNC, /* [25] - No Connect */ // NO CONNECT + GPIO_INNC, /* [26] - No Connect */ // NO CONNECT + GPIO_INNC, /* [27] - SW450-1 */ // MBREV0 + GPIO_INNC, /* [28] - SW450-2 */ // MBREV1 + GPIO_INNC, /* [29] - SW450-3 */ // MBREV2 + GPIO_INNC, /* [30] - SW450-4 */ // MBREV3 + GPIO_INNC, /* [31] - No Connect */ // NO CONNECT + GPIO_INNC, /* [32] - No Connect */ // NO CONNECT + GPIO_INNC, /* [33] - No Connect */ // NO CONNECT + GPIO_INNC, /* [34] - No Connect */ // NO CONNECT + GPIO_INNC, /* [35] - No Connect */ // NO CONNECT + GPIO_INNC, /* [36] - No Connect */ // NO CONNECT + GPIO_INNC, /* [37] - No Connect */ // NO CONNECT + GPIO_INNC, /* [38] - No Connect */ // NO CONNECT + GPIO_INNC, /* [39] - No Connect */ // NO CONNECT + GPIO_INNC, /* [40] - No Connect */ // NO CONNECT + GPIO_INNC, /* [41] - No Connect */ // NO CONNECT + GPIO_INNC, /* [42] - No Connect */ // NO CONNECT + GPIO_INNC, /* [43] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +};*/ + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gp_ssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, + //.core_dirq = &core_dedicated_irq, + //.sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/asrock/q1900m/irqroute.c b/src/mainboard/asrock/q1900m/irqroute.c new file mode 100644 index 0000000..df43ee9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h new file mode 100644 index 0000000..3944c9de --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +//#define TPAD_IRQ_OFFSET 0 +//#define TOUCH_IRQ_OFFSET 1 +//#define I8042_IRQ_OFFSET 2 +//#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +//#define TPAD_IRQ_GPIO 55 +//#define TOUCH_IRQ_GPIO 72 +//#define I8042_IRQ_GPIO 101 +//#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +//#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/mainboard.c b/src/mainboard/asrock/q1900m/mainboard.c new file mode 100644 index 0000000..09d807d --- /dev/null +++ b/src/mainboard/asrock/q1900m/mainboard.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <arch/acpi.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <smbios.h> +//#include <variant/onboard.h> +#include <soc/gpio.h> +#include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +//static void mainboard_init(struct device *dev) {} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + //dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c new file mode 100644 index 0000000..7a4d5a6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* I'm a bit desperate. */ + printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n"); + void *spd; + size_t spd_fsize; + + struct mrc_params mp = { + .mainboard = { + .dram_type = DRAM_DDR3, + .dram_info_location = DRAM_INFO_SPD_MEM, + .weaker_odt_settings = 1, + .dram_is_slotted = 1, + .spd_addrs = {0xf0, 0x00} + }, + }; + + spd = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + + if (!spd) + die("SPD data not found."); + + mp.mainboard.dram_data[0] = spd; + //mp.mainboard.dram_data[1] = spd; + + rp->mrc_params = &mp; + romstage_common(rp); +} diff --git a/src/mainboard/asrock/q1900m/spd/spd0.spd.hex b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asrock/q1900m/spd/spd1.spd.hex b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -- To view, visit https://review.coreboot.org/c/coreboot/+/39658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Gerrit-Change-Number: 39658 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: LinuxBoot: fix `make clean` for linux builds
by Alexander Couzens (Code Review) 05 Sep '23

05 Sep '23

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35438 ) Change subject: LinuxBoot: fix `make clean` for linux builds ...................................................................... LinuxBoot: fix `make clean` for linux builds The kernel_dir variable was never correct, because targets/linux.mk is using build directories based on the version e.g. kernel_4.19.73. Change-Id: I749200bd32d86303ae02903afd96f730ac36b307 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35438/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 5840e8e..8b81c8a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -14,7 +14,6 @@ ## project_dir=linuxboot -kernel_dir=$(project_dir)/kernel unexport $(COREBOOT_EXPORTS) @@ -65,7 +64,7 @@ linuxboot: kernel initramfs_compressed clean: - if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi + rm -rf $(project_dir)/kernel* rm -f $(project_dir)/u-root rm -f $(project_dir)/initramfs* -- To view, visit https://review.coreboot.org/c/coreboot/+/35438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749200bd32d86303ae02903afd96f730ac36b307 Gerrit-Change-Number: 35438 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

3 2

[S] Change in coreboot[master]: mb/google/brya/var/skolas: add nau8318 speaker support
by AlanKY Lee (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: David Lin, Eric Lai, Mac Chiang, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76925?usp=email ) Change subject: mb/google/brya/var/skolas: add nau8318 speaker support ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: Hi, Google please help to code review. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/76925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Gerrit-Change-Number: 76925 Gerrit-PatchSet: 20 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Lin <CTLIN0(a)nuvoton.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: David Lin <CTLIN0(a)nuvoton.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 23:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: add nau8318 speaker support
by AlanKY Lee (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: David Lin, Eric Lai, Mac Chiang, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76925?usp=email ) Change subject: mb/google/brya/var/skolas: add nau8318 speaker support ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > Yes, NAU8318 for SPK, NAU8825 for Headphone. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Gerrit-Change-Number: 76925 Gerrit-PatchSet: 20 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Lin <CTLIN0(a)nuvoton.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: David Lin <CTLIN0(a)nuvoton.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 23:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: add nau8318 speaker support
by AlanKY Lee (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: David Lin, Eric Lai, Mac Chiang, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76925?usp=email ) Change subject: mb/google/brya/var/skolas: add nau8318 speaker support ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > oh NAU8318 should be AMP not SPK? Yes, NAU8318 for SPK, NAU8825 for Headphone. -- To view, visit https://review.coreboot.org/c/coreboot/+/76925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Gerrit-Change-Number: 76925 Gerrit-PatchSet: 20 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Lin <CTLIN0(a)nuvoton.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: David Lin <CTLIN0(a)nuvoton.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 23:34:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Fix PMC GPIO group route to GPE
by Cliff Huang (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Anil Kumar K, Bora Guvendik, Eran Mitrani, Eric Lai, Hannah Williams, Ivy Jian, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Tarun Tuli, Wonkyu Kim. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76537?usp=email ) Change subject: mb/google/rex: Fix PMC GPIO group route to GPE ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb: https://review.coreboot.org/c/coreboot/+/76537/comment/20dc13b9_5c80355f : PS4, Line 24: none > `TPM_TIS_ACPI_INTERRUPT` is GPP E03. […] thx for pointing out. add missed bit description. For TPM_TIS_ACPI_INTERRUPT, it is not configured to route to SCI and its GPE0_EN is not set. However, its bit from GPE0_STS was checked, so I also add this pad. -- To view, visit https://review.coreboot.org/c/coreboot/+/76537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3bf27c71658f177c0ba544fb90712a82a058aa1 Gerrit-Change-Number: 76537 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 22:22:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Fix PMC GPIO group route to GPE
by Cliff Huang (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Hannah Williams, Ivy Jian, Jakub Czapiga, Jamie Ryu, Subrata Banik, Tarun, Tarun Tuli, Wonkyu Kim. Hello Anil Kumar K, Bora Guvendik, Eran Mitrani, Eric Lai, Ivy Jian, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Tarun Tuli, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76537?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Fix PMC GPIO group route to GPE ...................................................................... mb/google/rex: Fix PMC GPIO group route to GPE The defines in PMC should be used rather than the ones from GPIO defines. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ie3bf27c71658f177c0ba544fb90712a82a058aa1 --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/76537/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3bf27c71658f177c0ba544fb90712a82a058aa1 Gerrit-Change-Number: 76537 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
by Marshall Dawson (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76498?usp=email ) Change subject: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image ...................................................................... Patch Set 4: (13 comments) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76498/comment/77a020ff_051979ef : PS4, Line 75: config AMD_FWM_POSITION_INDEX : default 5 With no prompt, this won't be choosable by the developer via menuconfig. https://review.coreboot.org/c/coreboot/+/76498/comment/557342e2_1e12b84c : PS4, Line 93: config PSP_LOAD_MP2_FW Looks like unsupported in Epyc? So it could be omitted here. https://review.coreboot.org/c/coreboot/+/76498/comment/40fb4a01_737ade76 : PS4, Line 117: "3rdparty/amd_blobs_internal/genoa/PSP/wtl-gno.bin" Ideally this should be in "site-local/3rdparty/amd_blobs/genoa/PSP/wtl-gno.sbin" instead. https://review.coreboot.org/c/coreboot/+/76498/comment/0af7b8a0_0bbf9aad : PS4, Line 125: "3rdparty/amd_blobs_internal/genoa/PSP/PspDirL10_Typex55_BLAntiRB.bin Maybe 3rdparty/amd_blobs/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin? Is that the same one? https://review.coreboot.org/c/coreboot/+/76498/comment/8272db6b_3f6f178a : PS4, Line 137: Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) and here https://review.coreboot.org/c/coreboot/+/76498/comment/dd1b79e0_562e2b3f : PS4, Line 139: 55758 #57299 https://review.coreboot.org/c/coreboot/+/76498/comment/1ca1be35_5852e9bb : PS4, Line 156: Remove extra blank line https://review.coreboot.org/c/coreboot/+/76498/comment/c34668b6_8436eb6c : PS4, Line 157: endif : nit: for consistency maybe endif # SOC_AMD_GENOA File src/soc/amd/genoa/Makefile.inc: https://review.coreboot.org/c/coreboot/+/76498/comment/7e9550f2_f02a1450 : PS4, Line 23: PSPDIR ADDR | BIOSDIR ADDR If I'm reading the spec right BIOSDIR_ADDR may be 0x28. Or maybe the spec is ambiguous. https://review.coreboot.org/c/coreboot/+/76498/comment/c5ccf0a7_3b28d75b : PS4, Line 26: GENOA_FWM_POSITION=0x20000 Hmm, we seem to do MDN differently than other SOCs. Without taking the time to dig, it seems like this ought to be derived from the position index instead of hardcoded. https://review.coreboot.org/c/coreboot/+/76498/comment/c2c4b7d1_bd12b296 : PS4, Line 51: ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) : OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" : else : # Disable MP2 firmware loading : PSP_SOFTFUSE_BITS += 29 : endif remove, I think https://review.coreboot.org/c/coreboot/+/76498/comment/28708d61_b9dc1ec4 : PS4, Line 58: ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) : PSP_SOFTFUSE_BITS += 58 : endif remove https://review.coreboot.org/c/coreboot/+/76498/comment/89a0a7dc_944d0250 : PS4, Line 130: $(OPT_PSP_LOAD_MP2_FW) \ remove -- To view, visit https://review.coreboot.org/c/coreboot/+/76498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Gerrit-Change-Number: 76498 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 31 Aug 2023 22:18:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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