coreboot-gerrit June 2023

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[M] Change in coreboot[master]: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75564?usp=email ) Change subject: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge ...................................................................... soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge Now that Stoneyridge is the only AMD SoC that still needs the part of the SSDT that contains the TOM1 and TOM2, move it from the common code to the Stoneyridge northbridge code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9091360d6a82183092ef75417ad652523babe075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75564 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/stoneyridge/northbridge.c 3 files changed, 25 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index aaa851e..bda283a 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -3,9 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <amdblocks/acpi.h> -#include <amdblocks/chip.h> -#include <assert.h> -#include <cpu/amd/mtrr.h> #include <device/device.h> #include <types.h> @@ -15,28 +12,3 @@ { return acpi_write_hpet(device, current, rsdp); } - -/* Used by \_SB.PCI0._CRS */ -void acpi_fill_root_complex_tom(const struct device *device) -{ - const char *scope; - - assert(device); - - scope = acpi_device_scope(device); - assert(scope); - acpigen_write_scope(scope); - - acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); - - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); - acpigen_pop_len(); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 9105184..682f8ca 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -54,8 +54,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void acpi_fill_root_complex_tom(const struct device *device); - uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, uintptr_t current); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 452a7bb..90d227a 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -167,6 +167,31 @@ register_new_ioapic((u8 *)IO_APIC2_ADDR); } +/* Used by \_SB.PCI0._CRS */ +static void acpi_fill_root_complex_tom(const struct device *device) +{ + const char *scope; + + assert(device); + + scope = acpi_device_scope(device); + assert(scope); + acpigen_write_scope(scope); + + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); + acpigen_pop_len(); +} + static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; -- To view, visit https://review.coreboot.org/c/coreboot/+/75564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9091360d6a82183092ef75417ad652523babe075 Gerrit-Change-Number: 75564 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/glinda/chip: use common data fabric domain resource code
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75560?usp=email ) Change subject: soc/amd/glinda/chip: use common data fabric domain resource code ...................................................................... soc/amd/glinda/chip: use common data fabric domain resource code Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I948d882b2e2c6d19f73c0be094e4ff6e42ec81d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75560 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/acpi/pci0.asl M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/root_complex.c 4 files changed, 4 insertions(+), 63 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index d80eb3f..fe20591 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -46,6 +46,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl index 925f853..3f29c33 100644 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ b/src/soc/amd/glinda/acpi/pci0.asl @@ -5,15 +5,6 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ - - Method(_BBN, 0, NotSerialized) { - Return(0) /* Bus number = 0 */ - } - - Method(_STA, 0, NotSerialized) { - Return(0x0f) /* Status is visible */ - } /* Operating System Capabilities Method */ Method(_OSC, 4) { @@ -28,57 +19,6 @@ Return (Arg3) } } - Name(CRES, ResourceTemplate() { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 65c9e19..47794e6 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -28,10 +28,11 @@ }; struct device_operations glinda_pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amd_pci_domain_scan_bus, .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 9cb758a..071903d 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -220,7 +220,6 @@ static void root_complex_fill_ssdt(const struct device *device) { - acpi_fill_root_complex_tom(device); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948d882b2e2c6d19f73c0be094e4ff6e42ec81d6 Gerrit-Change-Number: 75560 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/phoenix/chip: use common data fabric domain resource code
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75559?usp=email ) Change subject: soc/amd/phoenix/chip: use common data fabric domain resource code ...................................................................... soc/amd/phoenix/chip: use common data fabric domain resource code Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. BUG=b:283495475 TEST=Myst still boots and both the coreboot console and the kernel show the expected PCI MMIO ranges being used. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I425876c4ef470574e00e123d36101641240c98cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/root_complex.c 4 files changed, 4 insertions(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 933043b..611b8a3 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -47,6 +47,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl index 345b66e..6039a5aa 100644 --- a/src/soc/amd/phoenix/acpi/pci0.asl +++ b/src/soc/amd/phoenix/acpi/pci0.asl @@ -5,15 +5,6 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ - - Method(_BBN, 0, NotSerialized) { - Return(0) /* Bus number = 0 */ - } - - Method(_STA, 0, NotSerialized) { - Return(0x0f) /* Status is visible */ - } /* Operating System Capabilities Method */ Method(_OSC, 4) { @@ -28,57 +19,6 @@ Return (Arg3) } } - Name(CRES, ResourceTemplate() { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index ee2c7cc..1bbb1b5 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -28,10 +28,11 @@ }; struct device_operations phoenix_pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amd_pci_domain_scan_bus, .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 3c754c6..f7c4c1e 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -220,7 +220,6 @@ static void root_complex_fill_ssdt(const struct device *device) { - acpi_fill_root_complex_tom(device); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I425876c4ef470574e00e123d36101641240c98cf Gerrit-Change-Number: 75559 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/mendocino/chip: use common data fabric domain resource code
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75558?usp=email ) Change subject: soc/amd/mendocino/chip: use common data fabric domain resource code ...................................................................... soc/amd/mendocino/chip: use common data fabric domain resource code Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/acpi/pci0.asl M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/root_complex.c 4 files changed, 4 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 41861ee..f372a4f 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -45,6 +45,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl index 5cc6f9f..3aa2aa8 100644 --- a/src/soc/amd/mendocino/acpi/pci0.asl +++ b/src/soc/amd/mendocino/acpi/pci0.asl @@ -5,15 +5,6 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ - - Method(_BBN, 0, NotSerialized) { - Return(0) /* Bus number = 0 */ - } - - Method(_STA, 0, NotSerialized) { - Return(0x0f) /* Status is visible */ - } /* Operating System Capabilities Method */ Method(_OSC, 4) { @@ -28,57 +19,6 @@ Return (Arg3) } } - Name(CRES, ResourceTemplate() { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 677b166..b3cbc74 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -26,10 +26,11 @@ }; struct device_operations mendocino_pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amd_pci_domain_scan_bus, .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 11f111f..492a588 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -373,8 +373,6 @@ { uint32_t tdp = 0; - acpi_fill_root_complex_tom(device); - if (get_amd_smu_reported_tdp(&tdp) != CB_SUCCESS) { /* Unknown TDP, so return rather than setting invalid values. */ return; -- To view, visit https://review.coreboot.org/c/coreboot/+/75558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18 Gerrit-Change-Number: 75558 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/cezanne/chip: use common data fabric domain resource code
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75557?usp=email ) Change subject: soc/amd/cezanne/chip: use common data fabric domain resource code ...................................................................... soc/amd/cezanne/chip: use common data fabric domain resource code Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/root_complex.c 4 files changed, 4 insertions(+), 63 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2975dda..e96169b 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index fb02a02..c778578 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -3,15 +3,6 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ - - Method(_BBN, 0, NotSerialized) { - Return(0) /* Bus number = 0 */ - } - - Method(_STA, 0, NotSerialized) { - Return(0x0f) /* Status is visible */ - } /* Operating System Capabilities Method */ Method(_OSC, 4) { @@ -26,57 +17,6 @@ Return (Arg3) } } - Name(CRES, ResourceTemplate() { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index d480cc5..9fd687b 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -26,10 +26,11 @@ }; struct device_operations cezanne_pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = amd_pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amd_pci_domain_scan_bus, .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index a4134ef..cb35662 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -190,7 +190,6 @@ static void root_complex_fill_ssdt(const struct device *device) { - acpi_fill_root_complex_tom(device); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Gerrit-Change-Number: 75557 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric/domain: write _BBN method in SSDT
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74992?usp=email ) Change subject: soc/amd/common/data_fabric/domain: write _BBN method in SSDT ...................................................................... soc/amd/common/data_fabric/domain: write _BBN method in SSDT Instead of having PCI0's _BBN method in the DSDT that always returns 0, use acpigen_write_BBN to generate the _BBN method that returns the first PCI bus number in the PCI domain/host bridge. TEST=On mandolin the _BBN method in the _SB/PCI0 scope is now in the SSDT instead of the DSDT, but still returns 0. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74992 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/picasso/acpi/northbridge.asl 2 files changed, 3 insertions(+), 5 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index aec1596..c032fdb 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -243,6 +243,9 @@ } acpigen_write_resourcetemplate_footer(); + + acpigen_write_BBN(domain->link_list->secondary); + /* Scope */ acpigen_pop_len(); } diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 688f138..2f73ae4 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -6,11 +6,6 @@ /* Describe the Northbridge devices */ -Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ -{ - Return(0) -} - Method(_STA, 0, NotSerialized) { Return(0x0f) /* Status is visible */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02 Gerrit-Change-Number: 74992 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/picasso/chip: use common data fabric domain resource code
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74712?usp=email ) Change subject: soc/amd/picasso/chip: use common data fabric domain resource code ...................................................................... soc/amd/picasso/chip: use common data fabric domain resource code Use amd_pci_domain_read_resources function that gets the configured MMIO regions for the PCI root domain from the data fabric's MMIO decode registers instead of using pci_domain_read_resources. This results in the same IO port range being used by the allocator, but makes sure that the allocator will only allocate non-fixed MMIO resources in the address ranges that get decoded to the PCI root complex. In order for the PCI0 _CRS ACPI resource template to match the decoded PCI root domain MMIO windows, use amd_pci_domain_fill_ssdt to generate the _CRS ACPI code instead of having a mostly hard-coded _CRS method in the DSDT. This makes sure that the OS will know about the MMIO regions it is allowed to used. Before this patch, only the region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS was advertised as usable PCI MMIO in the PCI0 _CRS method. Also the resource allocator didn't get any constraint on which address ranges it can use to put the non-fixed MMIO resources. This approach worked until now, since all address range from 0 up to right below TOM1 was filled with either usable or reserved memory and the allocator was allocating beginning right from TOM1, since it was using the bottom-up allocation approach and everything below TOM1 was already in use. The MMIO region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS also matched the MMIO decode window configured in the data fabric's MMIO decode registers, so everything seemed to work fine. However, when either selecting RESOURCE_ALLOCATION_TOP_DOWN or enabling above 4GB MMIO, things broke badly. This was partially due to the allocator putting non-fixed MMIO resources in regions that weren't decoded to the PCI root, since AMD family 17h and 19h silicon doesn't subtractively decode PCI MMIO and the wrong ranges the allocator used also weren't advertised in ACPI. TEST=Even when selecting RESOURCE_ALLOCATION_TOP_DOWN that usually ends up with a non-working system when the MMIO ranges aren't reported correctly to the resource allocator due to the reasons descried above, Ubuntu 22.04 LTS still boots on Mandolin both with SeaBIOS and EDK2 payload and Windows 10 boots with EDK payload. There's however an EDK2 bug that results the MMCONFIG region not being advertised in the e820 table, which causes Linux to not use the MMCONFIG and fall back to the legacy PCI config access method. This only happens with EDK2 payload and everything works fine when using SeaBIOS as payload. That e820 issue is unaffected by this patch. At the end of the data_fabric_set_mmio_np call, this is the data fabric MMIO register configuration: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 The limit of the data fabric MMIO decode register 1 is configured as 0xffffffffffff although this is way beyond the addressable memory space. add_data_fabric_mmio_regions fixes this up, so the range that gets passed to the allocator in that case is 0x7fcffffffff which takes both the reserved most significant address bits used for the memory encryption and the 12GB reserved data fabric MMIO at the top of the usable address space into account. This results in the following domain ranges passed to the resource allocator: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: fc000000 size: 0 align: 0 gran: 0 limit: febfffff DOMAIN: 0000 mem: base: 10000000000 size: 0 align: 0 gran: 0 limit: 7fcffffffff DOMAIN: 0000 mem: base: d0000000 size: 0 align: 0 gran: 0 limit: f7ffffff The IO resource producer region is split into two parts to not cover the PCI config IO region resource consumer. This results in these resources being added to the PCI0 _CRS resource template: amd_pci_domain_fill_ssdt ACPI scope: '\_SB.PCI0' PCI0 _CRS: adding busses [0-3f] PCI0 _CRS: adding IO range [0-cf7] PCI0 _CRS: adding IO range [d00-ffff] PCI0 _CRS: adding MMIO range [fc000000-febfffff] PCI0 _CRS: adding MMIO range [10000000000-7fcffffffff] PCI0 _CRS: adding MMIO range [d0000000-f7ffffff] PCI0 _CRS: adding VGA resource Kernel version 5.15.0-43 from Ubuntu 2022.4 LTS prints this in dmesg: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-3f] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff window] pci_bus 0000:00: root bus resource [mem 0xfc000000-0xfebfffff window] pci_bus 0000:00: root bus resource [mem 0x10000000000-0x7fcffffffff window] Another noteworthy thing I wasn't aware of at first when testing ACPI changes on Windows 10 is that a normal Windows shutdown and boot cycle won't result in it processing the changed ACPI tables; you have to tell it to reboot to do a proper full boot where it will process the updated ACPI tables (and fail if it dislikes something about the ACPI tables and bytecode). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74712 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/root_complex.c 5 files changed, 6 insertions(+), 80 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 11410ae..9738d19 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 99d04b5..688f138 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Note: Only need HID on Primary Bus */ -External (TOM1) -External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 1f2c0d9..898914c 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ioapic.h> - /* System Bus */ /* _SB.PCI0 */ @@ -23,74 +21,3 @@ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> #include <soc/amd/common/acpi/platform.asl> - -Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI buses can have 256 secondary buses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadOnly, - 0x00000000, 0x000c0000, 0x000dffff, 0x00000000, - 0x00020000) - - /* memory space for PCI BARs below 4GB */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) -}) /* End Name(_SB.PCI0.CRES) */ - -Method(_CRS, 0) { - /* Find PCI resource area in CRES */ - CreateDwordField (CRES, ^PM01._MIN, P1MN) - CreateDwordField (CRES, ^PM01._MAX, P1MX) - CreateDwordField (CRES, ^PM01._LEN, P1LN) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - P1MN = TOM1 - P1MX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 - P1LN = P1MX - P1MN + 1 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ -} /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 782c1c3..067c4a07 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -27,10 +27,11 @@ }; struct device_operations picasso_pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, - .acpi_name = soc_acpi_name, + .read_resources = amd_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = amd_pci_domain_scan_bus, + .acpi_name = soc_acpi_name, + .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 65021a3..7a83197 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -196,7 +196,6 @@ static void root_complex_fill_ssdt(const struct device *device) { - acpi_fill_root_complex_tom(device); if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2 Gerrit-Change-Number: 74712 Gerrit-PatchSet: 21 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74843?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt ...................................................................... soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI bus numbers and IO and MMIO regions can be used for PCI devices below _SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and amd_pci_domain_read_resources provided to the resource allocator. This makes sure that the PCI0 _CRS ACPI resource template matches the constraints the resource allocator used when allocating resources. TEST=With also the rest of the current patch train applied, the generated _CRS resource template contains the expected PCI bus numbers and IO and MMIO resources and both Linux and Windows boot on Mandolin. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74843 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h 2 files changed, 90 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 9b9ccc4..aec1596 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <console/console.h> #include <cpu/amd/mtrr.h> #include <device/device.h> @@ -158,3 +160,89 @@ add_data_fabric_mmio_regions(domain, &idx); } + +static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); + acpigen_resource_producer_io(base, limit); +} + +static void write_ssdt_domain_io_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + /* + * Split the IO region at the PCI config IO ports so that the IO resource producer + * won't cover the same IO ports that the IO resource consumer for the PCI config IO + * ports in the same ACPI device already covers. + */ + if (base < PCI_IO_CONFIG_INDEX) { + write_ssdt_domain_io_producer_range_helper(domain_name, + base, + MIN(limit, PCI_IO_CONFIG_INDEX - 1)); + } + if (limit > PCI_IO_CONFIG_LAST_PORT) { + write_ssdt_domain_io_producer_range_helper(domain_name, + MAX(base, PCI_IO_CONFIG_LAST_PORT + 1), + limit); + } +} + +static void write_ssdt_domain_mmio_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", + domain_name, base, limit); + acpigen_resource_producer_mmio(base, limit, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); +} + +void amd_pci_domain_fill_ssdt(const struct device *domain) +{ + const char *acpi_scope = acpi_device_path(domain); + printk(BIOS_DEBUG, "%s ACPI scope: '%s'\n", __func__, acpi_scope); + acpigen_write_scope(acpi_device_path(domain)); + + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + /* PCI bus number range in domain */ + printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x]\n", acpi_device_name(domain), + domain->link_list->secondary, domain->link_list->subordinate); + acpigen_resource_producer_bus_number(domain->link_list->secondary, + domain->link_list->subordinate); + + if (domain->link_list->secondary == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, + PCI_IO_CONFIG_PORT_COUNT, 1); + } + + struct resource *res; + for (res = domain->resource_list; res != NULL; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + return; + switch (res->flags & IORESOURCE_TYPE_MASK) { + case IORESOURCE_IO: + write_ssdt_domain_io_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + case IORESOURCE_MEM: + write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + default: + break; + } + } + + if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); + acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); + } + + acpigen_write_resourcetemplate_footer(); + /* Scope */ + acpigen_pop_len(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index c021f50..0ed3272 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -47,4 +47,6 @@ void amd_pci_domain_read_resources(struct device *domain); void amd_pci_domain_scan_bus(struct device *domain); +void amd_pci_domain_fill_ssdt(const struct device *domain); + #endif /* AMD_BLOCK_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Gerrit-Change-Number: 74843 Gerrit-PatchSet: 20 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_io
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75613?usp=email ) Change subject: acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_io ...................................................................... acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_io When an IO resource producer is generated that covers the whole IO space from 0 to 0xffff, the length field in the word resource ACPI type would overflow and be truncated which results in Linux not finding any usable IO space to use for the PCI IO BARs. Instead generate a double word IO resource producer to have all cases supported. Beware that covering all IO ports with the IO resource producer while covering the PCI config IO ports with a resource consumer in the same PCI root device will make Linux a bit unhappy and it will complain due to the overlap, but still end up doing the right thing: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored The SoC code should make sure to carve out the PCI config IO ports from the IO resource producer. TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord resource producer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 21b8ac1..fb92b89 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -2243,7 +2243,7 @@ void acpigen_resource_producer_io(u16 io_base, u16 io_limit) { - acpigen_resource_word(RSRC_TYPE_IO, /* res_type */ + acpigen_resource_dword(RSRC_TYPE_IO, /* res_type */ ADDR_SPACE_GENERAL_FLAG_MAX_FIXED | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED | ADDR_SPACE_GENERAL_FLAG_DEC_POS -- To view, visit https://review.coreboot.org/c/coreboot/+/75613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b Gerrit-Change-Number: 75613 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide scan_bus and read_resources
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74717?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide scan_bus and read_resources ...................................................................... soc/amd/common/data_fabric/domain: provide scan_bus and read_resources Provide amd_pci_domain_scan_bus to enumerate the PCI buses in the one PCI root domain and amd_pci_domain_read_resources to read the MMIO regions that the resource allocator can use to allocate the PCI MMIO BARs in the one PCI root domain from the corresponding data fabric MMIO decode registers. This makes sure that the allocator will only put PCI MMIO resources in areas that are decoded to the PCIe root complex. The current code only covers the case of a system with one PCI root where all PCI bus numbers belong to the only PCI root, all IO ports get decoded to the only PCI root and the MMIO regions from the data fabric MMIO decode registers get decoded to the only PCI root. In future patches, this will be extended to also support the multi PCI root case. TEST=With also the rest of the current patch train applied, the resource allocator uses the constraints on the MMIO regions and both Linux and Windows boot on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74717 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/data_fabric/Kconfig M src/soc/amd/common/block/data_fabric/Makefile.inc A src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h 4 files changed, 178 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/Kconfig b/src/soc/amd/common/block/data_fabric/Kconfig index 42cd6ec..c98bac4 100644 --- a/src/soc/amd/common/block/data_fabric/Kconfig +++ b/src/soc/amd/common/block/data_fabric/Kconfig @@ -3,3 +3,12 @@ help Select this option to add data fabric configuration related functionality to the build. + +config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN + bool + depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC + help + Select this option to add functionality to the build to tell the + resource allocator about the MMIO regions configured in the data + fabric registers so that it knows in which regions it can properly + allocate the non-fixed MMIO devices. diff --git a/src/soc/amd/common/block/data_fabric/Makefile.inc b/src/soc/amd/common/block/data_fabric/Makefile.inc index 1aa0308..868df82 100644 --- a/src/soc/amd/common/block/data_fabric/Makefile.inc +++ b/src/soc/amd/common/block/data_fabric/Makefile.inc @@ -1,6 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC),y) -ramstage-y += data_fabric_helper.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += data_fabric_helper.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += domain.c diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c new file mode 100644 index 0000000..9b9ccc4 --- /dev/null +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/cpu.h> +#include <amdblocks/data_fabric.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <types.h> + +void amd_pci_domain_scan_bus(struct device *domain) +{ + uint8_t bus, limit; + + /* TODO: Systems with more than one PCI root need to read the data fabric registers to + see which PCI bus numbers get decoded to which PCI root. */ + bus = 0; + limit = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1; + + /* Set bus first number of PCI root */ + domain->link_list->secondary = bus; + /* subordinate needs to be the same as secondary before pci_domain_scan_bus call. */ + domain->link_list->subordinate = bus; + + pci_domain_scan_bus(domain); + + /* pci_domain_scan_bus will modify subordinate, so change it back to the maximum + bus number decoded to this PCI root for the acpigen_resource_producer_bus_number + call to write the correct ACPI code. */ + domain->link_list->subordinate = limit; +} + +/* Read the registers and return normalized values */ +static void data_fabric_get_mmio_base_size(unsigned int reg, + resource_t *mmio_base, resource_t *mmio_limit) +{ + const uint32_t base_reg = data_fabric_broadcast_read32(0, DF_MMIO_BASE(reg)); + const uint32_t limit_reg = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(reg)); + /* The raw register values are bits 47..16 of the actual address */ + *mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT; + *mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1; +} + +static void print_df_mmio_outside_of_cpu_mmio_error(unsigned int reg) +{ + printk(BIOS_WARNING, "DF MMIO register %u outside of CPU MMIO region.\n", reg); +} + +static bool is_mmio_region_valid(unsigned int reg, resource_t mmio_base, resource_t mmio_limit) +{ + if (mmio_base > mmio_limit) { + printk(BIOS_WARNING, "DF MMIO register %u's base is above its limit.\n", reg); + return false; + } + if (mmio_base >= 4ULL * GiB) { + /* MMIO region above 4GB needs to be above TOP_MEM2 MSR value */ + if (mmio_base < get_top_of_mem_above_4gb()) { + print_df_mmio_outside_of_cpu_mmio_error(reg); + return false; + } + } else { + /* MMIO region below 4GB needs to be above TOP_MEM MSR value */ + if (mmio_base < get_top_of_mem_below_4gb()) { + print_df_mmio_outside_of_cpu_mmio_error(reg); + return false; + } + /* MMIO region below 4GB mustn't cross the 4GB boundary. */ + if (mmio_limit >= 4ULL * GiB) { + printk(BIOS_WARNING, "DF MMIO register %u crosses 4GB boundary.\n", + reg); + return false; + } + } + + return true; +} + +static void report_data_fabric_mmio(struct device *domain, unsigned int idx, + resource_t mmio_base, resource_t mmio_limit) +{ + struct resource *res; + res = new_resource(domain, idx); + res->base = mmio_base; + res->limit = mmio_limit; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; +} + +/* Tell the resource allocator about the usable MMIO ranges configured in the data fabric */ +static void add_data_fabric_mmio_regions(struct device *domain, unsigned int *idx) +{ + union df_mmio_control ctrl; + resource_t mmio_base; + resource_t mmio_limit; + + /* The last 12GB of the usable address space are reserved and can't be used for MMIO */ + const resource_t reserved_upper_mmio_base = + (1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE; + + for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { + ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i)); + + /* Relevant MMIO regions need to have both reads and writes enabled */ + if (!ctrl.we || !ctrl.re) + continue; + + /* Non-posted region contains fixed FCH MMIO devices */ + if (ctrl.np) + continue; + + /* TODO: Systems with more than one PCI root need to check to which PCI root + the MMIO range gets decoded to. */ + + data_fabric_get_mmio_base_size(i, &mmio_base, &mmio_limit); + + if (!is_mmio_region_valid(i, mmio_base, mmio_limit)) + continue; + + /* Make sure to not report a region overlapping with the fixed MMIO resources + below 4GB or the reserved MMIO range in the last 12GB of the addressable + address range. The code assumes that the fixed MMIO resources below 4GB + are between IO_APIC_ADDR and the 4GB boundary. */ + if (mmio_base < 4ULL * GiB) { + if (mmio_base >= IO_APIC_ADDR) + continue; + if (mmio_limit >= IO_APIC_ADDR) + mmio_limit = IO_APIC_ADDR - 1; + } else { + if (mmio_base >= reserved_upper_mmio_base) + continue; + if (mmio_limit >= reserved_upper_mmio_base) + mmio_limit = reserved_upper_mmio_base - 1; + } + + report_data_fabric_mmio(domain, (*idx)++, mmio_base, mmio_limit); + } +} + +/* Tell the resource allocator about the usable I/O space */ +static void add_io_regions(struct device *domain, unsigned int *idx) +{ + struct resource *res; + + /* TODO: Systems with more than one PCI root need to read the data fabric registers to + see which IO ranges get decoded to which PCI root. */ + + res = new_resource(domain, (*idx)++); + res->base = 0; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; +} + +void amd_pci_domain_read_resources(struct device *domain) +{ + unsigned int idx = 0; + + add_io_regions(domain, &idx); + + add_data_fabric_mmio_regions(domain, &idx); +} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index c224a11..c021f50 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -18,6 +18,9 @@ #define DF_MMIO_LIMIT(reg) (D18F0_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg)) #define DF_MMIO_CONTROL(reg) (D18F0_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg)) +/* Last 12GB of the usable address space are reserved */ +#define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB) + uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data); @@ -40,4 +43,8 @@ int data_fabric_find_unused_mmio_reg(void); void data_fabric_set_mmio_np(void); +/* Inform the resource allocator about the usable IO and MMIO regions and PCI bus numbers */ +void amd_pci_domain_read_resources(struct device *domain); +void amd_pci_domain_scan_bus(struct device *domain); + #endif /* AMD_BLOCK_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e Gerrit-Change-Number: 74717 Gerrit-PatchSet: 19 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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