coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74993?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope ...................................................................... soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Picasso more in line with Cezanne and newer SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef --- M src/soc/amd/picasso/acpi/northbridge.asl 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74993/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Gerrit-Change-Number: 74993 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/brya: Enable GPU ACPI for Hades
by Eric Lai (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75531?usp=email ) Change subject: mb/google/brya: Enable GPU ACPI for Hades ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774 Gerrit-Change-Number: 75531 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 00:42:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric/domain: write _STA method in SSDT
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has restored this change. ( https://review.coreboot.org/c/coreboot/+/74993?usp=email ) Change subject: soc/amd/common/data_fabric/domain: write _STA method in SSDT ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/74993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Gerrit-Change-Number: 74993 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: restore

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[XS] Change in coreboot[master]: mb/google/brya: Enable GPU ACPI for Hades
by Tarun Tuli (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75531?usp=email ) Change subject: mb/google/brya: Enable GPU ACPI for Hades ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/75531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774 Gerrit-Change-Number: 75531 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 00:35:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75597?usp=email ) Change subject: soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl ...................................................................... soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI code a bit more in line with the ACPI code of the other SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- R src/soc/amd/stoneyridge/acpi/mmio.asl M src/soc/amd/stoneyridge/acpi/soc.asl 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Raul Rangel: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl similarity index 100% rename from src/soc/amd/stoneyridge/acpi/sb_fch.asl rename to src/soc/amd/stoneyridge/acpi/mmio.asl diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index 47d5992..6e67f5a 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -15,8 +15,8 @@ /* Describe PCI INT[A-H] for the Southbridge */ #include "pci_int.asl" -/* Describe the devices in the Southbridge */ -#include "sb_fch.asl" +/* Describe the MMIO devices in the FCH */ +#include "mmio.asl" /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12 Gerrit-Change-Number: 75597 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75596?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/soc.asl 3 files changed, 5 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c47b7b7..af62abd 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -3,8 +3,6 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ /* Describe the Northbridge devices */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index a4903e9..08f7a31 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -7,21 +7,6 @@ /* System Bus */ /* _SB.PCI0 */ -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - /* Describe the Southbridge devices */ /* 0:14.0 - SMBUS */ diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index b411c20..47d5992 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/75596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Gerrit-Change-Number: 75596 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75591?usp=email ) Change subject: soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl ...................................................................... soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Picasso ACPI code a bit more in line with the ACPI code of the newer SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75591 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- R src/soc/amd/picasso/acpi/mmio.asl M src/soc/amd/picasso/acpi/soc.asl 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/mmio.asl similarity index 100% rename from src/soc/amd/picasso/acpi/sb_fch.asl rename to src/soc/amd/picasso/acpi/mmio.asl diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 0b520e4..a958570 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -19,8 +19,8 @@ /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> -/* Describe the devices in the Southbridge */ -#include "sb_fch.asl" +/* Describe the MMIO devices in the FCH */ +#include "mmio.asl" /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa Gerrit-Change-Number: 75591 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75590?usp=email ) Change subject: soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl ...................................................................... soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75590 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- D src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/soc.asl 2 files changed, 2 insertions(+), 9 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl deleted file mode 100644 index ead676d..0000000 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* System Bus */ -/* _SB.PCI0 */ - -/* 0:14.3 - LPC */ -#include <soc/amd/common/acpi/lpc.asl> -#include <soc/amd/common/acpi/platform.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 82c2766..0b520e4 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -9,7 +9,8 @@ #include "northbridge.asl" /* Describe the AMD Fusion Controller Hub */ - #include "sb_pci0_fch.asl" + #include <soc/amd/common/acpi/lpc.asl> + #include <soc/amd/common/acpi/platform.asl> } /* PCI IRQ mapping for the Southbridge */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75590?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774 Gerrit-Change-Number: 75590 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75569?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/picasso/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/picasso/acpi: use ROOT_BRIDGE macro Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. TEST=Both Ubuntu 2022.4 and Windows 10 still boot successfully and don't show any new ACPI-related error. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75569 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/soc.asl 3 files changed, 5 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 2f73ae4..5cbe950 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,9 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Note: Only need HID on Primary Bus */ -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - /* Describe the Northbridge devices */ Method(_STA, 0, NotSerialized) diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 898914c..ead676d 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -3,21 +3,6 @@ /* System Bus */ /* _SB.PCI0 */ -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> #include <soc/amd/common/acpi/platform.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index f44f873..82c2766 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/75569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f Gerrit-Change-Number: 75569 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75568?usp=email ) Change subject: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro ...................................................................... soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro When instantiated in the DSDT, this macro will expand to the static part of the PCIe root bridge device. This macro allows both to deduplicate parts of the DSDT code as well as adding more than one PCIe root bridge device in the DSDT. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75568 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/amd/common/acpi/pci_root.asl 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: Raul Rangel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/acpi/pci_root.asl b/src/soc/amd/common/acpi/pci_root.asl new file mode 100644 index 0000000..46d15b7 --- /dev/null +++ b/src/soc/amd/common/acpi/pci_root.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ROOT_BRIDGE(acpi_name) \ + Device(acpi_name) { \ + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ \ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ \ + Method (_OSC, 4, NotSerialized) { \ + /* Check for proper PCI/PCIe UUID */ \ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) \ + { \ + /* Let OS control everything */ \ + Return(Arg3) \ + } Else { \ + CreateDWordField(Arg3, 0, CDW1) \ + CDW1 = CDW1 | 4 /* Unrecognized UUID, so set bit 2 to 1 */ \ + Return(Arg3) \ + } \ + } \ + } -- To view, visit https://review.coreboot.org/c/coreboot/+/75568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Gerrit-Change-Number: 75568 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2023