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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> (.data. […]
okay, I see remove the static.
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> usb4_xhci_0/1 also?
(.data._dev_xhci_0+0x4c): undefined reference to `xhci_pci_ops'
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> I can help verify it.
usb4_xhci_0/1 also?
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> yeah, adding the device ops in the chipset devicetree would be the better way; that would also cover […]
CB:68148 is probably a good example of that approach
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> yeah, adding the device ops in the chipset devicetree would be the better way; that would also cover […]
I can help verify it.
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> hm, we should attach the driver to the device in the devicetree to significantly lower the chance of […]
yeah, adding the device ops in the chipset devicetree would be the better way; that would also cover devices 0x15BB, 0x15BD, 0x15C2 and 0x15C3
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
hm, we should attach the driver to the device in the devicetree to significantly lower the chance of missing this again in the next soc generation.
adding "ops xhci_pci_ops" right below "device pci 0.3 alias xhci_0 off" and the other 3 xhci controllers in the chipset devicetree should do the same and would also allow us to get rid of the pci id table. devices 0x15C0 and 0x15C1 are probably missing from this patch
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Patch Set 6:
(1 comment)
Patchset:
PS6:
friendly ping, could you help to push CR+2. thanks
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Change subject: soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS8:
> oh, right. […]
unabandoned the patch and updated it to only contain the part that drops the _STA method
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Change subject: soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scope
......................................................................
soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scope
The PCI root complex itself isn't on an enumerable bus, so without
providing an _STA method, the device will still be assumed to be present
and visible, so this won't change behavior. This also brings Stoneyridge
more in line with the newer SoCs.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028
---
M src/soc/amd/stoneyridge/acpi/northbridge.asl
1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75671/1
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl
index af62abd..6bf2293 100644
--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl
+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl
@@ -11,11 +11,6 @@
Return(0)
}
-Method(_STA, 0, NotSerialized)
-{
- Return(0x0F) /* Status is visible */
-}
-
Method(_PRT,0, NotSerialized)
{
If(PICM)
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