coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: vendorcode/amd/fsp/common: Refactor dmi_info.h
by Eric Lai (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Konrad Adamczyk, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email ) Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h ...................................................................... Patch Set 2: (1 comment) File src/vendorcode/amd/fsp/common/dmi_info.h: https://review.coreboot.org/c/coreboot/+/76107/comment/4d1db78f_b0e34cb2 : PS2, Line 144: } DMI_T17_MEMORY_TYPE; > That's valid point (in fact, more enums/structs defined in this file might be reused here). […] Yes, I agree. we can clean up if we have better idea. What I am trying to say is if something is defined in smbios, we can rely on smbios to decode. FSP can report the enum and just pass to cbmem dmi table, let coreboot to decode it. Assume the value is followed the smbios spec. SoC level todo is bypass the FSP mem_hob and fill the dmi_info. SoC don't need the detail here since FSP already do the job, and smbios will do it too. -- To view, visit https://review.coreboot.org/c/coreboot/+/76107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Gerrit-Change-Number: 76107 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 15:51:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Konrad Adamczyk <konrada(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vendorcode/amd/fsp/common: Refactor dmi_info.h
by Konrad Adamczyk (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel. Konrad Adamczyk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email ) Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h ...................................................................... Patch Set 2: (5 comments) Patchset: PS2: > I think we should list what's actually supported by coreboot, not the theoretical maximums supported […] Please let me know if I'm missing something here, but I'm not sure if we can do it this-straight-forward. There's a parsing code of this structure in [src/soc/amd/common/fsp/dmi.c](https://source.chromium.org/chromiumos/chromi… which heavily relies on compatibility between AGESA dmi_table layout and the coreboot one. Since the dmi.c iterates over the channel/dimms, decreasing values in there without doing same thing in AGESA could lead to missing some memory module entries to be reported by SMBIOS. File src/vendorcode/amd/fsp/common/dmi_info.h: https://review.coreboot.org/c/coreboot/+/76107/comment/f6f17287_ecb0c64e : PS2, Line 31: * This code was copied from src/vendorcode/amd/pi/00670F00/AGESA.h > Why remove the comment, and not extend it? I've removed it since it's no longer valid (as this is not a copy of the AGESA.h). I see your point to extend it, will fix it in v2. https://review.coreboot.org/c/coreboot/+/76107/comment/0a24894d_30e1c6d5 : PS2, Line 144: } DMI_T17_MEMORY_TYPE; > This is the same like https://source.chromium. […] That's valid point (in fact, more enums/structs defined in this file might be reused here). However, as the DMI_T17_MEMORY_TYPE is part of TYPE17_DMI_INFO structure and the [dmi.c](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:… relies heavily on FSP/AGESA structure compatibility, I'd rather keep TYPE17_DMI_INFO untouched (and not rely on external files to define it). File src/vendorcode/amd/fsp/glinda/soc_dmi_info.h: https://review.coreboot.org/c/coreboot/+/76107/comment/c6385edb_0ae30eb7 : PS2, Line 6: > Please add `/* TODO: Update for Glinda */` Done File src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h: https://review.coreboot.org/c/coreboot/+/76107/comment/c0cc53bf_e3549366 : PS2, Line 10: #define MAX_SOCKETS_SUPPORTED 4 ///< Max number of sockets in system : #define MAX_CHANNELS_PER_SOCKET 12 ///< Max Channels per sockets : #define MAX_DIMMS_PER_CHANNEL 2 ///< Max DIMMs on a memory channel (independent of platform) > MB Design guide for FP7/FP7R2: #56920 Rev1.06 […] I'm not sure how AGESA will report it for FP7/FP7R2, but as for FP8 (at least on Myst proto0) AGESA reports it as 4 separate channels. Those defines are used in parsing code of [dmi.c](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:…. However due to the fact that AGESA uses T17 struct of with 2 MAX_DIMMS_PER_CHANNEL, the scenario for `dmi.c` to report all four installed modules is to use 1/4/2 (at least) configuration. -- To view, visit https://review.coreboot.org/c/coreboot/+/76107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Gerrit-Change-Number: 76107 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 15:30:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi.c: Guard FACS generation
by Nico Huber (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76178?usp=email ) Change subject: acpi.c: Guard FACS generation ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76178/comment/ef9bf371_b203b614 : PS1, Line 2053: current = ALIGN_UP(current, 64); > Are you referring to the alignment? I'm not sure why it would even matter, I have never seen any ali […] It's right there in the second paragraph: "The platform boot firmware aligns the FACS on a 64-byte boundary anywhere within the system’s memory address space." -- To view, visit https://review.coreboot.org/c/coreboot/+/76178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Gerrit-Change-Number: 76178 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 15:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/vboot: Update vboot context with slot B absence
by Michał Żygowski (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Julius Werner. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75462?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/vboot: Update vboot context with slot B absence ...................................................................... security/vboot: Update vboot context with slot B absence coreboot offers two vboot schemes VBOOT_SLOTS_RW_A and VBOOT_SLOTS_RW_AB. When VBOOT_SLOTS_RW_AB is not selected then the resulting image is rather not expected to have RW_B flash regions. When only RW_A partition is used, vboot does additional full_reset cycles to try RW_B, even though it does not exist / the build was not configured for two RW partitions. To avoid it, a new vboot context flag has been introduced, VB2_CONTEXT_ONLY_ONE_SLOT, which can be set right after context initialization to inform vboot about absence of slot B. This will result in less full_reset cycles when vboot runs out of available slots and cause vboot to switch to recovery mode faster. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie123881a2f9f766ae65e4ac7c36bc2a8fce8d100 --- M src/security/vboot/vboot_logic.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/75462/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie123881a2f9f766ae65e4ac7c36bc2a8fce8d100 Gerrit-Change-Number: 75462 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86
by Tim Wawrzynczak (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Lance Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76070?usp=email ) Change subject: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86 ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76070/comment/a11d89e5_b8dfea91 : PS1, Line 161: if (ENV_X86) > We already have arch_fill_fadt(), I think it has worked out pretty well so perhaps introduce arch_fi […] +1 to `arch_fill_madt()` -- To view, visit https://review.coreboot.org/c/coreboot/+/76070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335 Gerrit-Change-Number: 76070 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 14:06:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi.c: Guard FACS generation
by Tim Wawrzynczak (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Lance Zhao, Nico Huber. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76178?usp=email ) Change subject: acpi.c: Guard FACS generation ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76178/comment/089db3a1_d44e074d : PS1, Line 2053: current = ALIGN_UP(current, 64); > This seems specific to FACS. Move this in the if block and […] Are you referring to the alignment? I'm not sure why it would even matter, I have never seen any alignment restrictions in the ACPI spec, nor have I seen problems with alignment of ACPI tables with non-coreboot firmware. But best to keep this the same unless it's tested. -- To view, visit https://review.coreboot.org/c/coreboot/+/76178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Gerrit-Change-Number: 76178 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 14:05:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Disable external fivr
by Mark Hsieh (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Derek Huang, Felix Held, Marco Chen, Shou-Chieh Hsu. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76187?usp=email ) Change subject: mb/google/nissa/var/joxer: Disable external fivr ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/76187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd7ad90e1544966170df402243604379f5790db Gerrit-Change-Number: 76187 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jun 2023 13:25:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/alderlake: Add support for Raptor Lake S CPUs
by Tim Crawford (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Bora Guvendik, Michał Żygowski, Michał Żygowski, Name of user not set #1004406, Paul Menzel, Subrata Banik. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69798?usp=email ) Change subject: soc/intel/alderlake: Add support for Raptor Lake S CPUs ...................................................................... Patch Set 14: (1 comment) File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/69798/comment/52c29dc9_d0f0a90d : PS14, Line 76: #define CPUID_RAPTORLAKE_S_A0 0xb0670 : #define CPUID_RAPTORLAKE_S_B0 0xb0671 : #define CPUID_RAPTORLAKE_S_C0_1 0xb0672 : #define CPUID_RAPTORLAKE_S_C0_2 0xb0675 : #define CPUID_RAPTORLAKE_P_J0 0xb06a2 : #define CPUID_RAPTORLAKE_P_Q0 0xb06a3 One question I had when doing HX was what to actually call these. They seem to be only related to the stepping and not the series they're a part of. Should `_S`/`_P`/`_HX` be dropped? -- To view, visit https://review.coreboot.org/c/coreboot/+/69798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 14 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Name of user not set #1004406 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 13:22:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig
by Michał Żygowski (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Felix Singer, Krystian Hebel, Michał Kopeć, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69825?usp=email ) Change subject: mb/msi/ms7d25: Configure ASPM and Clock PM based on Kconfig ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69825/comment/82602aed_afb4790b : PS3, Line 11: to achieve more deterministic and higher performance of PCIe devices > We did an iperf test on local network some time ago on PC Engines apu2. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/69825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Gerrit-Change-Number: 69825 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 12:59:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Michał Żygowski (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Himanshu Sahdev, Martin L Roth, Michał Kopeć, Nico Huber, Werner Zeh. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944?usp=email ) Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... Patch Set 17: (4 comments) File src/soc/intel/common/block/oc_wdt/Kconfig: https://review.coreboot.org/c/coreboot/+/68944/comment/ac903fbd_ec716dc4 : PS16, Line 7: config SOC_INTEL_COMMON_OC_WDT_ENABLE > I agree with Michał. It's also common to have one Kconfig to express SoC support […] Ping https://review.coreboot.org/c/coreboot/+/68944/comment/84f6abaf_155cb935 : PS16, Line 21: default 90 > LGTM. […] I have made the default high-enough to pass 128GB DDR5 memory to pass the training (even twice the time it needs, 128GB of DDR5 memory on ADL-S platform took around 5 minutes). Now SoCs can override the default per SoC needs, as the value is no longer exposed in the menuconfig. File src/soc/intel/common/block/oc_wdt/oc_wdt.c: https://review.coreboot.org/c/coreboot/+/68944/comment/0df1a0f0_afa17954 : PS17, Line 19: > /\* timeout - Time in seconds before WDT times out. […] Added a comment in code. https://review.coreboot.org/c/coreboot/+/68944/comment/1568d276_746bdd8d : PS17, Line 61: > /\* Returns time in seconds \*/ Added a comment in code. -- To view, visit https://review.coreboot.org/c/coreboot/+/68944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 12:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023