coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Device tree for Microtech etabpro Platform Intel GLK Tablet with the ...
by Miroslaw Kocur (Code Review) 10 Jun '23

10 Jun '23

Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40353 ) Change subject: Device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ...................................................................... Device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard Not working so far Fixed: - finally trying to start but not working yet Changes: - not much yet Change-Id: I154cb9abeba3e27cbb16acfd35012a996f099a92 Signed-off-by: Miroslaw Kocur <mirek190(a)gmail.com> --- M src/mainboard/microtech/etabpro/Kconfig M src/mainboard/microtech/etabpro/bootblock.c M src/mainboard/microtech/etabpro/etab.fmd M src/mainboard/microtech/etabpro/gpio.c M src/mainboard/microtech/etabpro/memory.c 5 files changed, 253 insertions(+), 220 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/40353/1 diff --git a/src/mainboard/microtech/etabpro/Kconfig b/src/mainboard/microtech/etabpro/Kconfig index aa7c106..716aadb 100644 --- a/src/mainboard/microtech/etabpro/Kconfig +++ b/src/mainboard/microtech/etabpro/Kconfig @@ -10,14 +10,29 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_LPC_TPM + select USE_BLOBS + select NEED_LBP2 + select LBP2_FROM_IFWI + select CONSOLE_SPI_FLASH # Blobs -# select NEED_IFWI -# select HAVE_IFD_BIN + select ADD_FSP_BINARIES +# select FSP_M_XIP +# select FSP_USE_REPO + select NEED_IFWI + select HAVE_IFD_BIN # config for GLK INTEL_EC # Not sure is VBOOT_NO_BOARD_SUPPORT is needed to work coreboot on GLK. Without it we got error if I choose GLK INTEL_EC... select EC_ACPI # select VBOOT_NO_BOARD_SUPPORT +config FSP_M_FILE + string + default "3rdparty/blobs/mainboard/microtech/etabpro/fspm.bin" + +config FSP_S_FILE + string + default "3rdparty/blobs/mainboard/microtech/etabpro/fsps.bin" + config IFWI_FILE string default "3rdparty/blobs/mainboard/microtech/etabpro/ifwi.bin" diff --git a/src/mainboard/microtech/etabpro/bootblock.c b/src/mainboard/microtech/etabpro/bootblock.c index 8f6f563..d17d0c3 100644 --- a/src/mainboard/microtech/etabpro/bootblock.c +++ b/src/mainboard/microtech/etabpro/bootblock.c @@ -26,5 +26,5 @@ lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - full_reset(); +// full_reset(); } diff --git a/src/mainboard/microtech/etabpro/etab.fmd b/src/mainboard/microtech/etabpro/etab.fmd index c71088a..c350ab2 100644 --- a/src/mainboard/microtech/etabpro/etab.fmd +++ b/src/mainboard/microtech/etabpro/etab.fmd @@ -1,7 +1,7 @@ FLASH 8M { SI_DESC 0x1000 SI_BIOS { - IFWI 0x2ff000 + IFWI 0x300000 OBBP { FMAP 0x1000 RO_FRID 0x40 diff --git a/src/mainboard/microtech/etabpro/gpio.c b/src/mainboard/microtech/etabpro/gpio.c index 71c0d16..19c17a1 100644 --- a/src/mainboard/microtech/etabpro/gpio.c +++ b/src/mainboard/microtech/etabpro/gpio.c @@ -22,222 +22,228 @@ * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { -/* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 1, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */ - PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */ - PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/ - PAD_CFG_GPI_APIC_IOS(GPIO_20, UP_20K, DEEP, LEVEL, INVERT, IGNORE, SAME),/* Audio Codec Interrupt*/ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */ - PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */ - PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Wake SCI */ - PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/ - PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */ - PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */ - PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */ - PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */ - PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SDA - Audio Codec*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SCL - Audio Codec */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SDA - NFC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SCL - NFC */ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SDA - Touch Pad*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SCL - Touch Pad*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RXD - M.2dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-TXD - M.2dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RTS_B - M.2 dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-CTS_B - M.2 dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */ -#if CONFIG(TPM_ON_FAST_SPI) - PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */ -#endif - PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/ - PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/ - PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/ - PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/ - PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/ - PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/ - PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/ - PAD_CFG_GPI_GPIO_DRIVER(GPIO_212, UP_20K, DEEP),/*Touch Panel Int*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/ -/* NORTH COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/ - PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/ - PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SCL*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/ - PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */ - PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/ - PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/ - PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ - PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/ - PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/ - PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/ - PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/ - PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ - PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/ - -/* AUDIO COMMUNITY GPIOS*/ - - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_BCLK*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_WS_SYNC*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, DN_20K, DEEP, NF2, HIZCRx1, SAME),/* AVS_I2S2_SDI*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_SD0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S1_MCLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1),/*AVS_M_CLK_A1*/ - PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1),/*AVS_M_DATA_1*/ - PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/ - -/* SCC COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD),/*SDCARD_CLK*/ - PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D1*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D2*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D3*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_CMD*/ - PAD_CFG_NF(GPIO_186, NONE, DEEP, NF1),/*SDCARD_CD_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, NONE, TxDRxE, SAME),/*SD Card*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), - PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/ - PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/ - PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/ - PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/ - PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/ - PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/ - PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/ - PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/ - PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/ - PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/ - PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/ - PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/ - PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/ - PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/ - PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/ + /* NORTHWEST COMMUNITY GPIOS */ + _PAD_CFG_STRUCT(GPIO_0, 0x44000700, 0x00c01000), // JTAG_TCK + _PAD_CFG_STRUCT(GPIO_1, 0x44000700, 0x00c01000), // JTAG_TRST_N + _PAD_CFG_STRUCT(GPIO_2, 0x44000700, 0x00c03000), // JTAG_TMS + _PAD_CFG_STRUCT(GPIO_3, 0x44000700, 0x00c03000), // JTAG_TDI + _PAD_CFG_STRUCT(GPIO_4, 0x44000700, 0x00c03000), // JTAG_TDO + _PAD_CFG_STRUCT(GPIO_5, 0x44000300, 0x00c3c000), // GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000402, 0x00c3f300), // JTAG_PREQ_N + _PAD_CFG_STRUCT(GPIO_7, 0x44000402, 0x00c3f300), // JTAG_PRDY_N + _PAD_CFG_STRUCT(GPIO_8, 0x04000300, 0x0003c032), // GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x04000300, 0x0003c033), // GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x04000300, 0x0003c034), // GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x04000300, 0x0003c035), // GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x04000300, 0x0003c036), // GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000300, 0x0003c037), // GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000300, 0x0003c038), // GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000300, 0x0003c039), // GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x42100102, 0x0002733d), // GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000300, 0x0003c03e), // GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000802, 0x0000303f), // CNV_MFUART2_RXD + _PAD_CFG_STRUCT(GPIO_22, 0x44000800, 0x00027040), // CNV_MFUART2_TXD + _PAD_CFG_STRUCT(GPIO_23, 0x44000802, 0x00003041), // CNV_GNSS_PA_BLANKING + _PAD_CFG_STRUCT(GPIO_24, 0x44000300, 0x0003c042), // GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000300, 0x0003c043), // GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x42800102, 0x00027044), // GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00003045), // GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000201, 0x00003246), // GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00023147), // GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x40900102, 0x0003f048), // GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x40800100, 0x0003f049), // GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000100, 0x0003d24a), // GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x40900102, 0x0003f04b), // GPIO + _PAD_CFG_STRUCT(GPIO_34, 0x44000201, 0x0003f34c), // GPIO + _PAD_CFG_STRUCT(GPIO_35, 0x44000201, 0x0003f34d), // GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000300, 0x0003c34e), // GPIO + _PAD_CFG_STRUCT(GPIO_37, 0x44000300, 0x0003c04f), // GPIO + _PAD_CFG_STRUCT(GPIO_38, 0x42880102, 0x0003f350), // GPIO + _PAD_CFG_STRUCT(GPIO_39, 0x44000201, 0x0003f351), // GPIO + _PAD_CFG_STRUCT(GPIO_40, 0x44000201, 0x0003f352), // GPIO + _PAD_CFG_STRUCT(GPIO_41, 0x44000300, 0x0003c053), // GPIO + _PAD_CFG_STRUCT(GPIO_42, 0x44000700, 0x00001054), // MDSI_A_TE + _PAD_CFG_STRUCT(GPIO_43, 0x44000702, 0x00001055), // MDSI_C_TE + _PAD_CFG_STRUCT(GPIO_44, 0x44000402, 0x00003356), // USB2_OC0_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x00003357), // USB2_OC1_N + _PAD_CFG_STRUCT(GPIO_46, 0x44000300, 0x0003c058), // GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000300, 0x0003c059), // GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000402, 0x0003e75a), // PMC_I2C_SDA + _PAD_CFG_STRUCT(GPIO_49, 0x44000402, 0x0003e75b), // PMC_I2C_SCL + _PAD_CFG_STRUCT(GPIO_50, 0x44000402, 0x0002275c), // SIO_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_51, 0x44000402, 0x0002275d), // SIO_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_52, 0x44000300, 0x0003c05e), // GPIO + _PAD_CFG_STRUCT(GPIO_53, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_54, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_55, 0x44000300, 0x0003c061), // GPIO + _PAD_CFG_STRUCT(GPIO_56, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_57, 0x44000300, 0x0003c063), // GPIO + _PAD_CFG_STRUCT(GPIO_58, 0x44000402, 0x00022764), // SIO_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_59, 0x44000402, 0x00022765), // SIO_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_60, 0x44000300, 0x0003c066), // GPIO + _PAD_CFG_STRUCT(GPIO_61, 0x44000300, 0x00003067), // GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x46880100, 0x0003c068), // GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), // GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000402, 0x0002336a), // SIO_UART2_RXD + _PAD_CFG_STRUCT(GPIO_65, 0x44000400, 0x0002336b), // SIO_UART2_TXD + _PAD_CFG_STRUCT(GPIO_66, 0x44000201, 0x0000336c), // GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), // GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000300, 0x0003c06e), // GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000300, 0x0003c06f), // GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000300, 0x0003c070), // GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000300, 0x0003c071), // GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000300, 0x0003c072), // GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000201, 0x0003f373), // GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000400, 0x0003f300), // THERMTRIP_N + _PAD_CFG_STRUCT(GPIO_75, 0x44000702, 0x00003000), // PROCHOT_N +// _PAD_CFG_STRUCT(GPIO_211, 0xffffffff, 0xffffffff), RESERVED + _PAD_CFG_STRUCT(GPIO_212, 0x44000102, 0x0001f375), // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000102, 0x0001d376), // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x0001d377), // GPIO + /* NORTH COMMUNITY GPIOS */ + _PAD_CFG_STRUCT(GPIO_76, 0x44000400, 0x0003c000), // SVID0_ALERT_N + _PAD_CFG_STRUCT(GPIO_77, 0x44000400, 0x0003c000), // SVID0_DATA + _PAD_CFG_STRUCT(GPIO_78, 0x44000400, 0x0003c000), // SVID0_CLK + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_81, 0x44000c02, 0x0003d034), // FST_SPI_CS2_N + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_84, 0x44000100, 0x00001037), // GPIO + _PAD_CFG_STRUCT(GPIO_85, 0x44000300, 0x00001038), // GPIO + _PAD_CFG_STRUCT(GPIO_86, 0x44000300, 0x00001039), // GPIO + _PAD_CFG_STRUCT(GPIO_87, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_88, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000502, 0x00003c3d), // FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_91, 0x44000300, 0x0003fc3e), // GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000500, 0x00003c3f), // FST_SPI_MOSI_IO + _PAD_CFG_STRUCT(GPIO_93, 0x44000502, 0x00003c40), // FST_SPI_MISO_IO + _PAD_CFG_STRUCT(GPIO_94, 0x44000502, 0x00003c41), // FST_SPI_IO2 + _PAD_CFG_STRUCT(GPIO_95, 0x44000502, 0x00003c42), // FST_SPI_IO3 + _PAD_CFG_STRUCT(GPIO_96, 0x44000500, 0x00003c43), // FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_97, 0x44000500, 0x00003c00), // FST_SPI_CLK_FB + _PAD_CFG_STRUCT(GPIO_98, 0x44000400, 0x0003c000), // PMU_PLTRST_N + _PAD_CFG_STRUCT(GPIO_99, 0x44000402, 0x0003f300), // PMU_PWRBTN_N + _PAD_CFG_STRUCT(GPIO_100, 0x44000400, 0x0003c000), // PMU_SLP_S0_N + _PAD_CFG_STRUCT(GPIO_101, 0x44000400, 0x0003c000), // PMU_SLP_S3_N + _PAD_CFG_STRUCT(GPIO_102, 0x44000400, 0x0003c000), // PMU_SLP_S4_N + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003c000), // SUSPWRDNACK + _PAD_CFG_STRUCT(GPIO_104, 0x44000700, 0x00003000), // EMMC_PWR_EN_N + _PAD_CFG_STRUCT(GPIO_105, 0x44000300, 0x0003c344), // GPIO + _PAD_CFG_STRUCT(GPIO_106, 0x44000402, 0x0003f300), // PMU_BATLOW_N + _PAD_CFG_STRUCT(GPIO_107, 0x44000400, 0x0003f300), // PMU_RSTBTN_N + _PAD_CFG_STRUCT(GPIO_108, 0x44000400, 0x0003c000), // PMU_SUSCLK + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), // SUS_STAT_N + _PAD_CFG_STRUCT(GPIO_110, 0x44000402, 0x0003e745), // SIO_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_111, 0x44000402, 0x0003e746), // SIO_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_112, 0x44000300, 0x0003c047), // GPIO + _PAD_CFG_STRUCT(GPIO_113, 0x44000300, 0x0003c048), // GPIO + _PAD_CFG_STRUCT(GPIO_114, 0x44000402, 0x00022749), // SIO_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_115, 0x44000402, 0x0002274a), // SIO_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0003f34b), // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c), // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_118, 0x44000402, 0x0003f34d), // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_119, 0x44000300, 0x0003c04e), // GPIO + _PAD_CFG_STRUCT(GPIO_120, 0x44000402, 0x0002334f), // PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_121, 0x44000402, 0x00023350), // PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00023351), // PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_123, 0x44000300, 0x00020352), // GPIO + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x0001c353), // DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x0001c354), // DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_126, 0x44000300, 0x0003c055), // GPIO + _PAD_CFG_STRUCT(GPIO_127, 0x44000300, 0x0003c056), // GPIO + _PAD_CFG_STRUCT(GPIO_128, 0x44000400, 0x00005257), // PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_129, 0x44000400, 0x00005258), // PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_130, 0x44000400, 0x00005259), // PNL0_BKLCTL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x0002735a), // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x0002735b), // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_133, 0x44000400, 0x0002435c), // DDI2_HPD + _PAD_CFG_STRUCT(GPIO_134, 0x44000201, 0x0003f35d), // GPIO + _PAD_CFG_STRUCT(GPIO_135, 0x44000201, 0x0000325e), // GPIO + _PAD_CFG_STRUCT(GPIO_136, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_137, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_138, 0x44000102, 0x00000061), // GPIO + _PAD_CFG_STRUCT(GPIO_139, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_140, 0x44000100, 0x00001063), // GPIO + _PAD_CFG_STRUCT(GPIO_141, 0x44001400, 0x00020364), // SATA_DEVSLP1 + _PAD_CFG_STRUCT(GPIO_142, 0x44900102, 0x00023365), // GPIO + _PAD_CFG_STRUCT(GPIO_143, 0x44900102, 0x00020066), // GPIO + _PAD_CFG_STRUCT(GPIO_144, 0x44000201, 0x00001067), // GPIO + _PAD_CFG_STRUCT(GPIO_145, 0x44000201, 0x00001068), // GPIO + _PAD_CFG_STRUCT(GPIO_146, 0x44001400, 0x00001069), // n/a + _PAD_CFG_STRUCT(GPIO_147, 0x44000702, 0x0000336a), // LPC_SERIRQ + _PAD_CFG_STRUCT(GPIO_148, 0x44000700, 0x0002006b), // LPC_CLKOUT0 + _PAD_CFG_STRUCT(GPIO_149, 0x44000700, 0x0002006c), // LPC_CLKOUT1 + _PAD_CFG_STRUCT(GPIO_150, 0x44000702, 0x0002336d), // LPC_AD0 + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), // LPC_AD1 + _PAD_CFG_STRUCT(GPIO_152, 0x44000702, 0x0002336f), // LPC_AD2 + _PAD_CFG_STRUCT(GPIO_153, 0x44000702, 0x00023370), // LPC_AD3 + _PAD_CFG_STRUCT(GPIO_154, 0x44000702, 0x00003071), // LPC_CLKRUN_N + _PAD_CFG_STRUCT(GPIO_155, 0x44000700, 0x00023372), // LPC_FRAME_N + /* Group Audio GPIOS */ + _PAD_CFG_STRUCT(GPIO_156, 0x42000100, 0x0003d200), // GPIO + _PAD_CFG_STRUCT(GPIO_157, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_158, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_159, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_160, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_162, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_163, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_165, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000400, 0x00021200), // AVS_HDA_BCLK + _PAD_CFG_STRUCT(GPIO_167, 0x44000400, 0x00021200), // AVS_HDA_WS_SYNC + _PAD_CFG_STRUCT(GPIO_168, 0x44000400, 0x00020000), // AVS_HDA_SDI + _PAD_CFG_STRUCT(GPIO_169, 0x44000400, 0x00021200), // AVS_HDA_SDO + _PAD_CFG_STRUCT(GPIO_170, 0x44000402, 0x00021200), // AVS_HDA_RST_N + _PAD_CFG_STRUCT(GPIO_171, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_172, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_173, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_174, 0x44000201, 0x00003300), // GPIO + _PAD_CFG_STRUCT(GPIO_175, 0x44000100, 0x00001000), // GPIO + /* Group SCC GPIOS */ + _PAD_CFG_STRUCT(GPIO_176, 0x40800102, 0x0003f000), // GPIO + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), // SMB_CLK + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), // SMB_DATA + _PAD_CFG_STRUCT(GPIO_187, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_179, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_180, 0x44000400, 0x00001200), // SDCARD_CLK_FB + _PAD_CFG_STRUCT(GPIO_181, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_182, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_184, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_185, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_186, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_188, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_210, 0x44000200, 0x0001f200), // GPIO + _PAD_CFG_STRUCT(GPIO_189, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000400, 0x0003c000), // CNV_BRI_DT + _PAD_CFG_STRUCT(GPIO_192, 0x44000402, 0x0003f300), // CNV_BRI_RST + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x0003c000), // CNV_RGI_DT + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x0003f300), // CNV_RGI_RST + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x0003c000), // CNV_RF_RESET_N + _PAD_CFG_STRUCT(GPIO_196, 0x44000400, 0x0003c000), // XTAL_CLKREQ + _PAD_CFG_STRUCT(GPIO_197, 0x44000b00, 0x00001200), // n/a + _PAD_CFG_STRUCT(GPIO_198, 0x44000400, 0x0001d200), // EMMC_CLK + _PAD_CFG_STRUCT(GPIO_199, 0x44000500, 0x00001200), // EMMC_D0 + _PAD_CFG_STRUCT(GPIO_200, 0x44000402, 0x00023300), // EMMC_D1 + _PAD_CFG_STRUCT(GPIO_201, 0x44000402, 0x00023300), // EMMC_D2 + _PAD_CFG_STRUCT(GPIO_202, 0x44000402, 0x00023300), // EMMC_D3 + _PAD_CFG_STRUCT(GPIO_203, 0x44000402, 0x00023300), // EMMC_D4 + _PAD_CFG_STRUCT(GPIO_204, 0x44000402, 0x00023300), // EMMC_D5 + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00023300), // EMMC_D6 + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00023300), // EMMC_D7 + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00023300), // EMMC_CMD + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00023300), // EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x0001d200), // EMMC_RST_N} }; + const struct pad_config * __weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -246,8 +252,8 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */ + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), /* SMB_CLK */ + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), /* SMB_DATA */ }; const struct pad_config * __weak diff --git a/src/mainboard/microtech/etabpro/memory.c b/src/mainboard/microtech/etabpro/memory.c index 2a4c43e..f74b29f 100644 --- a/src/mainboard/microtech/etabpro/memory.c +++ b/src/mainboard/microtech/etabpro/memory.c @@ -124,6 +124,18 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "H9HCNNN8KUMLHR", }, + /* 123456789012345678 - both logical channels */ + [6] = { + .speed = LP4_SPEED_2133, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "123456789012345678", + }, + [7] = { + .speed = LP4_SPEED_2133, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + }, }; static const struct lpddr4_cfg lp4cfg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/40353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I154cb9abeba3e27cbb16acfd35012a996f099a92 Gerrit-Change-Number: 40353 Gerrit-PatchSet: 1 Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/bd82x6x/elog.c: add missing power button events
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40346 ) Change subject: sb/intel/bd82x6x/elog.c: add missing power button events ...................................................................... sb/intel/bd82x6x/elog.c: add missing power button events Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I233575751c375172ac9dced10b6c13acc33e0445 --- M src/southbridge/intel/bd82x6x/elog.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40346/1 diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da79..99e3d9c 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -52,6 +52,10 @@ if (pm1_sts & (1 << 11)) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + /* Power Button */ + if (pm1_sts & (1 << 8)) + elog_add_event(ELOG_TYPE_POWER_BUTTON); + /* System Reset Status (reset button pushed) */ if (gen_pmcon_2 & (1 << 4)) elog_add_event(ELOG_TYPE_RESET_BUTTON); @@ -69,6 +73,9 @@ * Wake sources */ + /* Power Button */ + if (pm1_sts & (1 << 8)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/40346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I233575751c375172ac9dced10b6c13acc33e0445 Gerrit-Change-Number: 40346 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Doc/mb/asus: Add H110M-E/M.2 Documentation
by Pavel Sayekat (Code Review) 10 Jun '23

10 Jun '23

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35011 ) Change subject: Doc/mb/asus: Add H110M-E/M.2 Documentation ...................................................................... Doc/mb/asus: Add H110M-E/M.2 Documentation Followed and adapted from the ASRock H110M-DVS Documentation Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b --- A Documentation/mainboard/asus/h110m-e_m2.md 1 file changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35011/1 diff --git a/Documentation/mainboard/asus/h110m-e_m2.md b/Documentation/mainboard/asus/h110m-e_m2.md new file mode 100644 index 0000000..134dca8 --- /dev/null +++ b/Documentation/mainboard/asus/h110m-e_m2.md @@ -0,0 +1,136 @@ +# ASUS H110M-E/M.2 + +This page describes how to run coreboot on the [ASUS H110M-E/M.2]. + +## Required proprietary blobs + +Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). + +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +## Building coreboot + +The following steps set the default parameters for this board to build a +fully working image: + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_ASUS +./util/scripts/config --enable BOARD_ASUS_H110M_E_M2 +./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES +./util/scripts/config --enable CONFIG_FSP_USE_REPO +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" +make olddefconfig +``` + +However, it is strongly advised to use `make menuconfig` afterwards +(or instead), so that you can see all of the settings. + +Use the following command to disable the serial console if debugging +output is not required: + +```bash +./util/scripts/config --disable CONSOLE_SERIAL +``` + +However, a more flexible method is to change the console log level from +within an OS using `util/nvramtool`, or with the `nvramcui` payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region, such as the Management Engine or firmware descriptor, then +an external programmer is required (unless you find a clever way around +the flash protection). More information about this [here](../../flash_tutorial/index.md). + +### External programming + +The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a +GIgaDevice GD25B128CPIG, whose datasheet can be found [here][GD25B128CPIG]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.3 (Motherboard Layout) of the +[H110M-E/M.2 manual], where the chip is labelled "128Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported. + +- SuperIO GPIO pin is used to reset Realtek chip. However, since the + Logical Device 7 (GPIO7, GPIO8) is not initialized, the network + chip is in a reset state all the time. + +## Untested + +- parallel port +- PS/2 keyboard +- PS/2 mouse +- EHCI debug +- TPM +- infrared module +- chassis intrusion header +- chassis speaker header + +## Working + +- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) +- PCIe x1 +- PEG x16 Gen3 +- SATA +- USB +- serial port +- onboard audio +- using `me_cleaner` +- using `flashrom` + +## TODO + +- NCT5539D GPIOs +- onboard network (see [Known issues](#known-issues)) +- S3 suspend/resume +- Wake-on-LAN +- hardware monitor + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Skylake/Kaby Lake (LGA1151) | ++------------------+--------------------------------------------------+ +| PCH | Intel Sunrise Point H110 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT5539D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASUS H110M-E/M.2]: https://www.asus.com/Motherboards/H110M-E-M-2/overview/ +[GD25B128CPIG]: https://www.gigadevice.com/datasheet/gd25b127d/ [The closest match found] +[flashrom]: https://flashrom.org/Flashrom +[ASUS H110M-E/M.2 manual]: https://dlcdnets.asus.com/pub/ASUS/mb/LGA1151/H110M-E_M2/E11622_H110M-E_M2_… -- To view, visit https://review.coreboot.org/c/coreboot/+/35011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b Gerrit-Change-Number: 35011 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: include/elog.h: add intruder detection event codes
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40342 ) Change subject: include/elog.h: add intruder detection event codes ...................................................................... include/elog.h: add intruder detection event codes Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3a1cd17bb7e12271adef0ef3d505509f25d4c87a --- M src/include/elog.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40342/1 diff --git a/src/include/elog.h b/src/include/elog.h index 68a4842..5a7632d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -195,6 +195,11 @@ /* Cr50 reset to enable TPM */ #define ELOG_TYPE_CR50_NEED_RESET 0xb2 +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + struct elog_event_extended_event { u8 event_type; u32 event_complement; -- To view, visit https://review.coreboot.org/c/coreboot/+/40342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a1cd17bb7e12271adef0ef3d505509f25d4c87a Gerrit-Change-Number: 40342 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: commonlib/elog: Add missing PCI Express PME sources
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40417 ) Change subject: commonlib/elog: Add missing PCI Express PME sources ...................................................................... commonlib/elog: Add missing PCI Express PME sources Intel Skylake SoC defines more than 12 PCI Express wake sources. However, these wake sources are not defined anywhere. Without these definitions the coreboot build for Skylake or Kaby Lake board fails when event log is enabled. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc --- M src/commonlib/include/commonlib/elog.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40417/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h index 3b84242..c9b0c3e 100644 --- a/src/commonlib/include/commonlib/elog.h +++ b/src/commonlib/include/commonlib/elog.h @@ -166,6 +166,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { uint8_t source; @@ -383,6 +395,18 @@ { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE13, "PCI Express 13 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE14, "PCI Express 14 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE15, "PCI Express 15 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE16, "PCI Express 16 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE17, "PCI Express 17 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE18, "PCI Express 18 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE19, "PCI Express 19 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE20, "PCI Express 20 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE21, "PCI Express 21 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE22, "PCI Express 22 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE23, "PCI Express 23 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE24, "PCI Express 24 PME" }, { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc Gerrit-Change-Number: 40417 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: util/cbmem: implement event log parser
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40344 ) Change subject: util/cbmem: implement event log parser ...................................................................... util/cbmem: implement event log parser Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia24bc23e99f12ca4bd57505f83351a2907f81a33 --- M util/cbmem/cbmem.c 1 file changed, 213 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/40344/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f8da7da..d318acb 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -32,6 +32,7 @@ #include <assert.h> #include <regex.h> #include <commonlib/cbmem_id.h> +#include <commonlib/elog.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/tcpa_log_serialized.h> #include <commonlib/coreboot_tables.h> @@ -1080,6 +1081,207 @@ unmap_memory(&coverage_mapping); } + +static int bcd_to_decimal(uint8_t x) +{ + return x - 6 * (x >> 4); +} + +static char *get_name_from_table(const struct elog_event_name *event_table, u8 event) +{ + size_t table_size; + + if (event_table == elog_event_to_name) + table_size = ARRAY_SIZE(elog_event_to_name); + else if (event_table == elog_ec_event_to_name) + table_size = ARRAY_SIZE(elog_ec_event_to_name); + else if (event_table == elog_wake_event_to_name) + table_size = ARRAY_SIZE(elog_wake_event_to_name); + else if (event_table == elog_ec_device_event_to_name) + table_size = ARRAY_SIZE(elog_ec_device_event_to_name); + else if (event_table == mrc_upd_slots) + table_size = ARRAY_SIZE(mrc_upd_slots); + else + return "Unknown"; + + for (size_t i = 0; i < table_size; i++) { + if (event_table[i].event_type == event) + return event_table[i].event_name; + } + return "Unknown event type"; +} + +static void print_raw(uint8_t *start, size_t end) +{ + size_t i, j; + for (i = 0; i < end; i += 16) { + for (j = 0; j < 16; j++) { + if (i + j >= end) + break; + printf("%02x ", start[i+j]); + } + printf("\n"); + } +} + +static void print_elog_date(struct event_header *ev_header) +{ + printf("[20%02d-%02d-%02d %02d:%02d:%02d] ", + bcd_to_decimal(ev_header->year), + bcd_to_decimal(ev_header->month), + bcd_to_decimal(ev_header->day), + bcd_to_decimal(ev_header->hour), + bcd_to_decimal(ev_header->minute), + bcd_to_decimal(ev_header->second)); +} + +struct cbmem_elog { + u32 magic; + u8 version; + u8 header_size; + u8 reserved[2]; +} __attribute__ ((__packed__)); + +static void dump_elog(void) +{ + uint64_t start; + size_t size, offset; + const void *elog; + uint8_t *elog_data; + size_t elog_size; + struct mapping elog_mapping; + struct cbmem_elog *cb_elog; + struct event_header *ev_header; + struct elog_event_data_wake *wake_ev; + struct elog_event_data_me_extended *me_ext_ev; + struct elog_event_mem_cache_update *mrc_event; + struct elog_event_extended_event *elog_ext; + + if (find_cbmem_entry(CBMEM_ID_ELOG, &start, &size)) { + fprintf(stderr, "ELOG area not found\n"); + return; + } + + elog = map_memory(&elog_mapping, start, size); + if (!elog) + die("Unable to map elog area.\n"); + + cb_elog = (struct cbmem_elog *)elog; + + printf("Dumping ELOG data...\n"); + printf("ELOG version %d\n", cb_elog->version); + + offset = cb_elog->header_size; + + while (*(uint8_t *)(elog + offset) != ELOG_TYPE_EOL) { + ev_header = (struct event_header *)(elog + offset); + print_elog_date(ev_header); + printf("%s", get_name_from_table(elog_event_to_name, ev_header->type)); + + elog_data = (uint8_t *) (elog + offset + sizeof(struct event_header)); + elog_size = ev_header->length - sizeof(struct event_header) - 1; + + if (ev_header->type < 0x80) { + offset += ev_header->length; + if (elog_size != 0) { + printf(". Data: "); + print_raw(elog_data, elog_size); + } else { + printf("\n"); + } + continue; + } + + switch (ev_header->type) { + case ELOG_TYPE_EC_EVENT: + printf(": %s\n", + get_name_from_table(elog_ec_event_to_name, *elog_data)); + break; + case ELOG_TYPE_ACPI_ENTER: + case ELOG_TYPE_ACPI_WAKE: + printf(": S%d\n", bcd_to_decimal(*elog_data)); + break; + case ELOG_TYPE_WAKE_SOURCE: + wake_ev = (struct elog_event_data_wake *) + (elog + offset + sizeof(struct event_header)); + printf(": %s instance %d\n", + get_name_from_table(elog_wake_event_to_name, wake_ev->source), + wake_ev->instance); + break; + case ELOG_TYPE_MEM_CACHE_UPDATE: + mrc_event = (struct elog_event_mem_cache_update *) + (elog + offset + sizeof(struct event_header)); + printf(": slot %s, status %s\n", + get_name_from_table(mrc_upd_slots, mrc_event->slot), + mrc_event->status ? "FAIL" : "SUCCESS"); + break; + case ELOG_TYPE_EC_DEVICE_EVENT: + printf(": %s\n", get_name_from_table(elog_ec_device_event_to_name, + *elog_data)); + break; + case ELOG_TYPE_EXTENDED_EVENT: + elog_ext = (struct elog_event_extended_event *) + (elog + offset + sizeof(struct event_header)); + if (elog_ext->event_type == ELOG_SLEEP_PENDING_PM1_WAKE) + printf(": Pending PM1 wake (%08d)\n", + elog_ext->event_complement); + else if (elog_ext->event_type == ELOG_SLEEP_PENDING_GPE0_WAKE) + printf(": Pending GPE0 wake (%08d)\n", + elog_ext->event_complement); + else + printf(": Unknown (%08d)\n", elog_ext->event_complement); + break; + case ELOG_TYPE_CROS_RECOVERY_MODE: + printf(": reason %02x\n", *elog_data); + break; + case ELOG_TYPE_INTRUDER_DETECTION: + if (*elog_data == ELOG_CASE_OPENED) + printf(": Case opened\n"); + else if (*elog_data == ELOG_CASE_CLOSED) + printf(": Case closed\n"); + else + printf(": Unknown (%02x)\n", *elog_data); + break; + case ELOG_TYPE_MANAGEMENT_ENGINE: + if (*elog_data < 6) + printf(": %s\n", me_bios_paths[*elog_data]); + else + printf("Unknown\n"); + break; + case ELOG_TYPE_MANAGEMENT_ENGINE_EXT: + me_ext_ev = (struct elog_event_data_me_extended *) + (elog + offset + sizeof(struct event_header)); + printf(":\n" + "\t\t\tCurrent working state: %02x\n" + "\t\t\tOperation state: %02x\n" + "\t\t\tOperation mode: %02x\n" + "\t\t\tError code: %02x\n" + "\t\t\tProgress code: %02x\n" + "\t\t\tCurrent PM event: %02x\n" + "\t\t\tCurrent state: %02x\n", + me_ext_ev->current_working_state, + me_ext_ev->operation_state, + me_ext_ev->operation_mode, + me_ext_ev->error_code, + me_ext_ev->progress_code, + me_ext_ev->current_pmevent, + me_ext_ev->current_state); + break; + default: + if (elog_size != 0) { + printf(": Unknown. Data: "); + print_raw(elog_data, elog_size); + } else + printf("\n"); + break; + } /* switch */ + + offset += ev_header->length; + } /* while */ + + unmap_memory(&elog_mapping); +} + static void print_version(void) { printf("cbmem v%s -- ", CBMEM_VERSION); @@ -1101,6 +1303,7 @@ " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" " -C | --coverage: dump coverage information\n" + " -e | --elog: dump event log\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" " -r | --rawdump ID: print rawdump of specific ID (in hex) of cbtable\n" @@ -1234,6 +1437,7 @@ int print_defaults = 1; int print_console = 0; int print_coverage = 0; + int print_elog = 0; int print_list = 0; int print_hexdump = 0; int print_rawdump = 0; @@ -1248,6 +1452,7 @@ {"console", 0, 0, 'c'}, {"oneboot", 0, 0, '1'}, {"coverage", 0, 0, 'C'}, + {"elog", 0, 0, 'e'}, {"list", 0, 0, 'l'}, {"tcpa-log", 0, 0, 'L'}, {"timestamps", 0, 0, 't'}, @@ -1259,13 +1464,17 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c1CltTLxVvh?r:", + while ((opt = getopt_long(argc, argv, "c1CeltTLxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': print_console = 1; print_defaults = 0; break; + case 'e': + print_elog = 1; + print_defaults = 0; + break; case '1': print_console = 1; one_boot_only = 1; @@ -1401,6 +1610,9 @@ if (print_coverage) dump_coverage(); + if (print_elog) + dump_elog(); + if (print_list) dump_cbmem_toc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/40344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia24bc23e99f12ca4bd57505f83351a2907f81a33 Gerrit-Change-Number: 40344 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: ec/google/chromeec: Add support for USB Type-C alternate mode control
by John Zhao (Code Review) 10 Jun '23

10 Jun '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40424 ) Change subject: ec/google/chromeec: Add support for USB Type-C alternate mode control ...................................................................... ec/google/chromeec: Add support for USB Type-C alternate mode control PMC mux control can be used for swapping the USB data role and for setting connector to act in alternate modes. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along with PMC mux control. Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40424/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 3e9b773..a8d859f 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -56,4 +56,117 @@ { Return (0xB) } + + Device (USBC) + { + Name (_HID, "GOOG0014") + Name (_DDN, "ChromeOS Embedded Controller USB Type-C Control") + + /* + * Each connector shall have its own ACPI device entry + * (node), under the actual interface device. + */ + Device (CON0) + { + Name (_ADR, 0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + } + }) + + /* + * Each supported alternate mode. Use _STA() to disable/enable + * them. + */ + + /* Thunderbolt 3 alternate mode */ + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0x8087 }, + Package () { "vdo", 1 }, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Display Port alternate mode */ + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + }, + }) + + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () {"svid", 0x8087}, + Package () {"vdo", 1}, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Gerrit-Change-Number: 40424 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: sb/intel/common/smihandler.c: add mainboard intrusion detection handler
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40348 ) Change subject: sb/intel/common/smihandler.c: add mainboard intrusion detection handler ...................................................................... sb/intel/common/smihandler.c: add mainboard intrusion detection handler Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b --- M src/southbridge/intel/common/smihandler.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40348/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..b8ea9a2 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -424,6 +424,9 @@ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); + } else if (tco_sts & (1 << 16)) { /* INTRUDER */ + mainboard_smi_intruder(tco_sts); + printk(BIOS_DEBUG, "TCO Intruder.\n"); } else { dump_tco_status(tco_sts); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b Gerrit-Change-Number: 40348 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH
by Edward O'Callaghan (Code Review) 10 Jun '23

10 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40517 ) Change subject: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH ...................................................................... mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH Unfortunately EC_ENABLE_LID_SWITCH needs to be toggled on to enable the 'PNP0C0D' ASL device on otherwise the wake pin will not be noticed by the kernel. This patch works around that issue for Puff and Puff variants. BUG=b:152913653 BRANCH=none TEST=builds Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/duffy/include/variant/ec.h M src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40517/1 diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Gerrit-Change-Number: 40517 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: print all Lewisburg GPIO registers
by Maxim Polyakov (Code Review) 10 Jun '23

10 Jun '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40014 ) Change subject: util/inteltool: print all Lewisburg GPIO registers ...................................................................... util/inteltool: print all Lewisburg GPIO registers These changes are in accordance with the documentation: [*] "Intel C620 Series Chipset Platform Controller Hub", datasheet. May 2019. Document Number: 336067-007US Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/gpio_names/lewisburg.h 1 file changed, 220 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40014/1 diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h index 4d59177..d2aba7a 100644 --- a/util/inteltool/gpio_names/lewisburg.h +++ b/util/inteltool/gpio_names/lewisburg.h @@ -4,10 +4,190 @@ #include "gpio_groups.h" #include "sunrise.h" +static const struct gpiocom_register lewisburg_community0_abf_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_A_0"}, + {0x24, "PAD_OWN_GPP_A_1"}, + {0x28, "PAD_OWN_GPP_A_2"}, + {0x2C, "PAD_OWN_GPP_B_0"}, + {0x30, "PAD_OWN_GPP_B_1"}, + {0x34, "PAD_OWN_GPP_B_2"}, + {0x38, "PAD_OWN_GPP_F_0"}, + {0x3C, "PAD_OWN_GPP_F_1"}, + {0x40, "PAD_OWN_GPP_F_2"}, + {0x60, "PADCFGLOCK_GPP_A"}, + {0x64, "PADCFGLOCKTX_GPP_A"}, + {0x68, "PADCFGLOCK_GPP_B"}, + {0x6C, "PADCFGLOCKTX_GPP_B"}, + {0x70, "PADCFGLOCK_GPP_F"}, + {0x74, "PADCFGLOCKTX_GPP_F"}, + {0x80, "HOSTSW_OWN_GPP_A"}, + {0x84, "HOSTSW_OWN_GPP_B"}, + {0x88, "HOSTSW_OWN_GPP_F"}, + {0x100, "GPI_IS_GPP_A"}, + {0x104, "GPI_IS_GPP_B"}, + {0x108, "GPI_IS_GPP_F"}, + {0x110, "GPI_IE_GPP_A"}, + {0x114, "GPI_IE_GPP_B"}, + {0x118, "GPI_IE_GPP_F"}, + {0x120, "GPI_GPE_STS_GPP_A"}, + {0x124, "GPI_GPE_STS_GPP_B"}, + {0x128, "GPI_GPE_STS_GPP_F"}, + {0x130, "GPI_GPE_EN_GPP_A"}, + {0x134, "GPI_GPE_EN_GPP_B"}, + {0x138, "GPI_GPE_EN_GPP_F"}, + {0x144, "GPI_SMI_STS_GPP_B"}, + {0x154, "GPI_SMI_EN_GPP_B"}, + {0x164, "GPI_NMI_STS_GPP_B"}, + {0x174, "GPI_NMI_EN_GPP_B"}, +}; + +static const struct gpiocom_register lewisburg_community1_cde_cfg_registers[] = { + {0x10, "PADBAR"}, + {0x13, "MISCCFG"}, + {0x23, "PAD_OWN_GPP_C_0"}, + {0x24, "PAD_OWN_GPP_C_1"}, + {0x28, "PAD_OWN_GPP_C_2"}, + {0x2C, "PAD_OWN_GPP_D_0"}, + {0x30, "PAD_OWN_GPP_D_1"}, + {0x34, "PAD_OWN_GPP_D_2"}, + {0x38, "PAD_OWN_GPP_E_0"}, + {0x3C, "PAD_OWN_GPP_E_1"}, + {0x60, "PADCFGLOCK_GPP_C_0"}, + {0x64, "PADCFGLOCKTX_GPP_C_0"}, + {0x68, "PADCFGLOCK_GPP_D_0"}, + {0x6C, "PADCFGLOCKTX_GPP_D_0"}, + {0x70, "PADCFGLOCK_GPP_E_0"}, + {0x74, "PADCFGLOCKTX_GPP_E_0"}, + {0x80, "HOSTSW_OWN_GPP_C_0"}, + {0x84, "HOSTSW_OWN_GPP_D_0"}, + {0x88, "HOSTSW_OWN_GPP_E_0"}, + {0x100, "GPI_IS_GPP_C_0"}, + {0x104, "GPI_IS_GPP_D_0"}, + {0x108, "GPI_IS_GPP_E_0"}, + {0x110, "GPI_IE_GPP_C_0"}, + {0x114, "GPI_IE_GPP_D_0"}, + {0x118, "GPI_IE_GPP_E_0"}, + {0x120, "GPI_GPE_STS_GPP_C_0"}, + {0x124, "GPI_GPE_STS_GPP_D_0"}, + {0x128, "GPI_GPE_STS_GPP_E_0"}, + {0x130, "GPI_GPE_EN_GPP_C_0"}, + {0x134, "GPI_GPE_EN_GPP_D_0"}, + {0x138, "GPI_GPE_EN_GPP_E_0"}, + {0x140, "GPI_SMI_STS_GPP_C_0"}, + {0x144, "GPI_SMI_STS_GPP_D_0"}, + {0x148, "GPI_SMI_STS_GPP_E_0"}, + {0x150, "GPI_SMI_EN_GPP_C_0"}, + {0x154, "GPI_SMI_EN_GPP_D_0"}, + {0x158, "GPI_SMI_EN_GPP_E_0"}, + {0x160, "GPI_NMI_STS_GPP_C_0"}, + {0x164, "GPI_NMI_STS_GPP_D_0"}, + {0x168, "GPI_NMI_STS_GPP_E_0"}, + {0x170, "GPI_NMI_EN_GPP_C_0"}, + {0x174, "GPI_NMI_EN_GPP_D_0"}, + {0x178, "GPI_NMI_EN_GPP_E_0"}, + {0x204, "PWMC"}, + {0x20C, "GP_SER_BLINK"}, + {0x210, "GP_SER_CMDSTS"}, + {0x214, "GP_SER_DATA"}, +}; + +static const struct gpiocom_register lewisburg_community2_gpd_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPD_0"}, + {0x24, "PAD_OWN_GPD_1"}, + {0x60, "PADCFGLOCK_GPD_0"}, + {0x64, "PADCFGLOCKTX_GPD_0"}, + {0x80, "HOSTSW_OWN_GPD_0"}, + {0x100, "GPI_IS_GPD_0"}, + {0x110, "GPI_IE_GPD_0"}, + {0x120, "GPI_GPE_STS_GPD_0"}, + {0x130, "GPI_GPE_EN_GPD_0"}, +}; + +static const struct gpiocom_register lewisburg_community3_i_cfg_registers[] = { + {0xC0, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_I_0"}, + {0x24, "PAD_OWN_GPP_I_1"}, + {0x60, "PADCFGLOCK_GPP_I_0"}, + {0x64, "PADCFGLOCKTX_GPP_I_0"}, + {0x80, "HOSTSW_OWN_GPP_I_0"}, + {0x100, "GPI_IS_GPP_I_0"}, + {0x110, "GPI_IE_GPP_I_0"}, + {0x120, "GPI_GPE_STS_GPP_I_0"}, + {0x130, "GPI_GPE_EN_GPP_I_0"}, + {0x140, "GPI_SMI_STS_GPP_I_0"}, + {0x150, "GPI_SMI_EN_GPP_I_0"}, + {0x160, "GPI_NMI_STS_GPP_I_0"}, + {0x170, "GPI_NMI_EN_GPP_I_0"}, +}; + +static const struct gpiocom_register lewisburg_community4_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_J_0"}, + {0x24, "PAD_OWN_GPP_J_1"}, + {0x28, "PAD_OWN_GPP_J_2"}, + {0x2C, "PAD_OWN_GPP_K_0"}, + {0x30, "PAD_OWN_GPP_K_1"}, + {0x60, "PADCFGLOCK_GPP_J"}, + {0x64, "PADCFGLOCKTX_GPP_J"}, + {0x68, "PADCFGLOCK_GPP_K"}, + {0x6C, "PADCFGLOCKTX_GPP_K"}, + {0x80, "HOSTSW_OWN_GPP_J"}, + {0x84, "HOSTSW_OWN_GPP_K"}, + {0x100, "GPI_IS_GPP_J"}, + {0x104, "GPI_IS_GPP_K"}, + {0x110, "GPI_IE_GPP_J"}, + {0x114, "GPI_IE_GPP_K"}, + {0x120, "GPI_GPE_STS_GPP_J"}, + {0x124, "GPI_GPE_STS_GPP_K"}, + {0x130, "GPI_GPE_EN_GPP_J"}, + {0x134, "GPI_GPE_EN_GPP_K"}, +}; + +static const struct gpiocom_register lewisburg_community5_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_G_0"}, + {0x24, "PAD_OWN_GPP_G_1"}, + {0x28, "PAD_OWN_GPP_G_2"}, + {0x2C, "PAD_OWN_GPP_H_0"}, + {0x30, "PAD_OWN_GPP_H_1"}, + {0x34, "PAD_OWN_GPP_H_2"}, + {0x38, "PAD_OWN_GPP_L_0"}, + {0x3C, "PAD_OWN_GPP_L_1"}, + {0x40, "PAD_OWN_GPP_L_2"}, + {0x60, "PADCFGLOCK_GPP_G"}, + {0x64, "PADCFGLOCKTX_GPP_G"}, + {0x68, "PADCFGLOCK_GPP_H"}, + {0x6C, "PADCFGLOCKTX_GPP_H"}, + {0x70, "PADCFGLOCK_GPP_L"}, + {0x74, "PADCFGLOCKTX_GPP_L"}, + {0x80, "HOSTSW_OWN_GPP_G"}, + {0x84, "HOSTSW_OWN_GPP_H"}, + {0x88, "HOSTSW_OWN_GPP_L"}, + {0x100, "GPI_IS_GPP_G"}, + {0x104, "GPI_IS_GPP_H"}, + {0x108, "GPI_IS_GPP_L"}, + {0x110, "GPI_IE_GPP_G"}, + {0x114, "GPI_IE_GPP_H"}, + {0x118, "GPI_IE_GPP_L"}, + {0x120, "GPI_GPE_STS_GPP_G"}, + {0x124, "GPI_GPE_STS_GPP_H"}, + {0x128, "GPI_GPE_STS_GPP_L"}, + {0x130, "GPI_GPE_EN_GPP_G"}, + {0x134, "GPI_GPE_EN_GPP_H"}, + {0x138, "GPI_GPE_EN_GPP_L"}, +}; + static const char *const lewisburg_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_,A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_,A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_,A2", "LAD1", "n/a", "ESPI_IO1", "GPP_A3", "LAD2", "n/a", "ESPI_IO2", "GPP_A4", "LAD3", "n/a", "ESPI_IO3", "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", @@ -384,10 +564,12 @@ }; static const struct gpio_community lewisburg_community0_abf = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), - .groups = lewisburg_community0_abf_groups, + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .groups = lewisburg_community0_abf_groups, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .cfg_registers = lewisburg_community0_abf_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community0_abf_cfg_registers), }; static const struct gpio_group *const lewisburg_community1_cde_groups[] = { @@ -397,10 +579,12 @@ }; static const struct gpio_community lewisburg_community1_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), - .groups = lewisburg_community1_cde_groups, + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .groups = lewisburg_community1_cde_groups, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .cfg_registers = lewisburg_community1_cde_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community1_cde_cfg_registers), }; static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { @@ -408,10 +592,12 @@ }; static const struct gpio_community lewisburg_community2_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), - .groups = lewisburg_community2_gpd_groups, + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .groups = lewisburg_community2_gpd_groups, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .cfg_registers = lewisburg_community2_gpd_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community2_gpd_cfg_registers), }; static const struct gpio_group *const lewisburg_community3_i_groups[] = { @@ -419,10 +605,12 @@ }; static const struct gpio_community lewisburg_community3_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), - .groups = lewisburg_community3_i_groups, + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .groups = lewisburg_community3_i_groups, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .cfg_registers = lewisburg_community3_i_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community3_i_cfg_registers), }; static const struct gpio_group *const lewisburg_community4_jk_groups[] = { @@ -431,10 +619,12 @@ }; static const struct gpio_community lewisburg_community4_jk = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0xab, - .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), - .groups = lewisburg_community4_jk_groups, + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .groups = lewisburg_community4_jk_groups, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), }; static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { @@ -444,10 +634,13 @@ }; static const struct gpio_community lewisburg_community5_ghl = { - .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x11, - .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), - .groups = lewisburg_community5_ghl_groups, + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .groups = lewisburg_community5_ghl_groups, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), + }; static const struct gpio_community *const lewisburg_communities[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/40014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Gerrit-Change-Number: 40014 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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