coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: asrock/imb-a180: Add comment about label on chip
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22227?usp=email ) Change subject: asrock/imb-a180: Add comment about label on chip ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/22227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54226cbca9ce7eb8927fc4dfd1cbe5e061c705d Gerrit-Change-Number: 22227 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP] Documentation/basics: Add glossary
by Christoph Pomaska (Code Review) 10 Jun '23

10 Jun '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35911 ) Change subject: [WIP] Documentation/basics: Add glossary ...................................................................... [WIP] Documentation/basics: Add glossary The glossary is to contain common abbreviations and specific vocabulary. Change-Id: I2ef9130f9cfecacdc0033deba3cde582fb991f54 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A Documentation/basics/glossary.md 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35911/1 diff --git a/Documentation/basics/glossary.md b/Documentation/basics/glossary.md new file mode 100644 index 0000000..f820bf1 --- /dev/null +++ b/Documentation/basics/glossary.md @@ -0,0 +1,27 @@ +# Glossary + +## Intro +This page explains the most common abbreviations and terms. It also contains additional reference for some more detailed info. + +## Intel-specific + +- IFD: Intel Flash Descriptor\ + The Intel Flash Descriptor is used on Intel platforms to split the contents of a flash chip into multiple parts (regions). + Most boards contain the following regions: + * ifd + * me + * gbe + * bios + * platform data +- ME: Intel Management Engine + The Intel Management Engine is a co-processor that runs proprietary code which resides next to the bios-firmware within the "me" flash-region. + On older platforms it is possible to disable the ME by removing the code from the flash-chip. Since Sandybridge it is only possible to disable the ME by removing most parts of it and making it crash on startup, disabling a watchdog that shuts off the whole system 30 minutes after startup. Since Skylake it not possible to remove anything from the ME without breaking it. +- GbE: Gigabit Ethernet + This regions contains a firmware blob for Intel Gigabit Ethernet hardware. It is usually not used for mainboards that dont have Intel Gigabit ethernet onboard. +- BIOS: Basic Input Output System + The BIOS region contains the firmware that is required to boot up and initialize the system/mainboard. This is the region where coreboot is usually written to. + +## coreboot-specific +- CBFS: coreboot file system + The coreboot filesystem contains the files that are require for coreboot to work, such as the bootblock, payloads and romstage/ramstage binaries. + -- To view, visit https://review.coreboot.org/c/coreboot/+/35911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef9130f9cfecacdc0033deba3cde582fb991f54 Gerrit-Change-Number: 35911 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add basics section
by Christoph Pomaska (Code Review) 10 Jun '23

10 Jun '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35910 ) Change subject: Documentation: Add basics section ...................................................................... Documentation: Add basics section As discussed on the coreboot mailing list, I decided to create a section called "basics" for basic hard- and software information and documentation. Change-Id: Ia7d3b4c6ee203708d4058c4e52550e1ed24c64d1 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A Documentation/basics/index.md 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35910/1 diff --git a/Documentation/basics/index.md b/Documentation/basics/index.md new file mode 100644 index 0000000..a3ebff7 --- /dev/null +++ b/Documentation/basics/index.md @@ -0,0 +1,8 @@ +# basic and general information about hardware + +This section contains basic information and documentation about hardware +that a coreboot dev has to deal with. + +## x86 +* [Super I/O](superio.md) + -- To view, visit https://review.coreboot.org/c/coreboot/+/35910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7d3b4c6ee203708d4058c4e52550e1ed24c64d1 Gerrit-Change-Number: 35910 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [WIP]Documentation: Port graphics initialization from wiki
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/26781?usp=email ) Change subject: [WIP]Documentation: Port graphics initialization from wiki ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/26781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3212af27fb44c6d975fe9def4864d4d027086003 Gerrit-Change-Number: 26781 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: Fix potential NULL pointer dereferences and memory leak
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30098?usp=email ) Change subject: Fix potential NULL pointer dereferences and memory leak ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a8910e68b7a8ce0e97ca4cdb9ef7f595c0e319 Gerrit-Change-Number: 30098 Gerrit-PatchSet: 4 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: Documentation/contributing/project_ideas.md: add resource allocation ...
by Jeremy Soller (Code Review) 10 Jun '23

10 Jun '23

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39455 ) Change subject: Documentation/contributing/project_ideas.md: add resource allocation project ...................................................................... Documentation/contributing/project_ideas.md: add resource allocation project Change-Id: I278ee622be2ab4a3d26bd5a180e7471236a828b8 --- M Documentation/contributing/project_ideas.md 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/39455/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2c621f4..4198501 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -184,3 +184,15 @@ ### Mentors * TODO + +## Implement 64-bit resource allocation +Currently the coreboot allocator is limited to 32-bit allocation, which can be +problematic for systems with a large number of memory-mapped devices, or +devices with large memory regions, or hot-pluggable buses. + +### Requirements +* Understand the basics of PCI resource allocation, and be willing to learn + more about coreboot's resource allocation. + +### Mentors +* Jeremy Soller <jeremy(a)system76.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/39455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278ee622be2ab4a3d26bd5a180e7471236a828b8 Gerrit-Change-Number: 39455 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/ifdtool: modify IFD regions
by Marcello Sylvester Bauer (Code Review) 10 Jun '23

10 Jun '23

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38832 ) Change subject: Documentation/ifdtool: modify IFD regions ...................................................................... Documentation/ifdtool: modify IFD regions Add documentation about using ifdtool to modify the region rangers, with examples. Change-Id: I862bd851fc68365ca11aa0477ae4e4002f1eeea7 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M Documentation/ifdtool/layout.md 1 file changed, 53 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38832/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f..c09cfaa 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -4,7 +4,7 @@ layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md). -The FMAP should define all of the of the regions defined by the IFD to ensure +The FMAP should define all offsets of the regions defined by the IFD to ensure that those regions are accounted for by coreboot and will not be accidentally modified. @@ -23,7 +23,7 @@ |4|Platform Data|SI_PDR|| |8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash| -## Validation +## Modification The ifdtool can be used to manipulate a firmware image with a IFD. This tool will not take into account the FMAP while modifying the image which can lead to @@ -32,6 +32,56 @@ ME, then when the ME is added by the ifdtool 6 MB will be written which could overwrite 2 MB of the BIOS. +### Manual Modification + +It is possible to adjust the IFD regions on a firmware image or on a Flash Descriptor file directly. +In the case of modifying a complete firmware image, it will also move the data content of each region. + +The process consists of three steps: + 1) dump the ifd layout file out of the firmware/descriptor image + 2) modify the ifd region defined on the layout file + 3) update the firmware/descriptor image using the new layout + +#### Example - Reduce the ME Region size + +##### Step 1 - Dump IFD regions into a flashrom layout file + $ ifdtool -f ifd_old.layout descriptor.bin + Wrote layout to ifd-old.layout + + $ cat ifd_old.layout + 00000000:00000fff fd + 00500000:007fffff bios + 00003000:004fffff me + 00001000:00002fff gbe + +##### Step 2 - Modify the layout file + $ diff ifd_old.layout ifd_new.layout + 2,3c2,3 + < 00500000:007fffff bios + < 00003000:004fffff me + --- + > 00020000:007fffff bios + > 00003000:0001ffff me + +##### Step 3 - Update the IFD regions + $ ifdtool -n ifd_new.layout descriptor.bin + [...] + Writing new image to descriptor.bin.new + +### build-time Modification + +Instead of using the the ifdtool directly, it is possible to define a flashrom layout file in the +coreboot configuration, so that it will be modified at build-time. + + $ make menuconfig + Chipset ---> + [*] Add Intel descriptor.bin file + (path/to/descriptor.bin) Path and filename of the descriptor.bin file + [*] update regions using a flashrom layout file + (path/to/ifd.layout) Path and filename flashrom layout file + +## Validation + In order to validate that the FMAP and the IFD are compatible the ifdtool provides --validate (-t) option. `ifdtool -t` will read both the IFD and the FMAP in the image and for every non empty region in the IFD if that region is @@ -63,4 +113,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/38832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bd851fc68365ca11aa0477ae4e4002f1eeea7 Gerrit-Change-Number: 38832 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/d945gclf: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40205 ) Change subject: mb/intel/d945gclf: Remove ACPI generic sleep button SLPB ...................................................................... mb/intel/d945gclf: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 6.429967] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input2 [ 6.437520] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device. Fixes: 1a08f582 ("preliminary Intel D945GCLF Atom+i945 support.") Change-Id: I0174bffe53bcc9f86db793e2a05f6e95d86dbd10 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/intel/d945gclf/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40205/1 diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 5187b2a..bb86c6c 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -12,14 +12,6 @@ * GNU General Public License for more details. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0174bffe53bcc9f86db793e2a05f6e95d86dbd10 Gerrit-Change-Number: 40205 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Felix Singer (Code Review) 10 Jun '23

10 Jun '23

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39830 to review the following change. Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from platform data. This is also necessary if the PIT is dis- abled, which is the default, for instance, on Coffee Lake CPUs. Change-Id: I34eed1cbf14a8bf3fe6d58f51a4be139f4d30759 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 58 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39830/1 diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index bf0c30a..6b07e17 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -34,6 +34,10 @@ #include <libpayload.h> #include <arch/rdtsc.h> +#include <arch/cpuid.h> +#include <arch/msr.h> + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -46,7 +50,7 @@ * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -72,7 +76,59 @@ * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Returns three times the bus clock in MHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + uint32_t eax, ebx, ecx, edx; + cpuid(1, eax, ebx, ecx, edx); + + /* Check for family 6 */ + if (((eax & 0xff00000) >> (20 - 4)) | ((eax & 0xf00) >> 8 != 6)) + return -1; + + switch (((eax & 0xf0000) >> (16 - 4)) | ((eax & 0xf0) >> 4)) { + case 0x25: /* Nehalem */ + return 400 * 1000; /* 133 MHz */ + case 0x2a: /* SandyBridge */ + case 0x3a: /* IvyBridge */ + case 0x3c: /* Haswell */ + case 0x45: /* Haswell-ULT */ + case 0x9e: /* Coffee Lake H */ + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ +static int get_cpu_khz_fast(void) +{ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return (bus_x3 * mult) / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eed1cbf14a8bf3fe6d58f51a4be139f4d30759 Gerrit-Change-Number: 39830 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40204 ) Change subject: mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB ...................................................................... mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 5.162651] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input1 [ 5.163192] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device (intel/d945gclf). Fixes: be913983 ("mb/gigabyte/ga-945gcm-s2l: add mainboard") Change-Id: I36803d0f437e6556c5bdc82f2fd0ceb0562bc935 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40204/1 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl index 1e31c06..4c37212 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl @@ -1,14 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36803d0f437e6556c5bdc82f2fd0ceb0562bc935 Gerrit-Change-Number: 40204 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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