coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/intel/jasperlake: Enable Cnvi based on dev enabled
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41512?usp=email ) Change subject: soc/intel/jasperlake: Enable Cnvi based on dev enabled ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/41512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77fd7dd58826fab78cea67302feb17329cd8c783 Gerrit-Change-Number: 41512 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [UNTESTED] intel/stm: Introduce stm_update_smm_info()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

3 6

Change in coreboot[master]: [UNTESTED] cpu/x86/smm: Drop now unused `num_cpus` param
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

3 2

Change in coreboot[master]: [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Kyösti Mälkki, Aaron Durbin, Arthur Heymans, cedarhouse1(a)comcast.net, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38769 to review the following change. Change subject: [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info() ...................................................................... [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info() Also keep related calculations local to STM code. Change-Id: I3aa5915ddeffdabe792b9c30cd72cc39a8f54ca6 --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/security/intel/stm/SmmStm.h M src/security/intel/stm/StmPlatformSmm.c 4 files changed, 39 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38769/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5b34d4b..45f7337 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -746,22 +746,8 @@ /* Setup code checks this callback for validity. */ mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); - if (CONFIG(STM)) { - if (is_smm_enabled()) { - uintptr_t mseg; - - mseg = mp_state.perm_smbase + - (mp_state.perm_smsize - CONFIG_MSEG_SIZE); - - stm_setup(mseg, p->cpu, - perm_smbase, - mp_state.perm_smbase, - runtime->start32_offset); - } else { - printk(BIOS_DEBUG, - "STM not loaded because SMM is not enabled!\n"); - } - } + stm_setup(cpu, mp_state.perm_smbase, mp_state.perm_smsize, + perm_smbase, runtime->start32_offset); } static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index d4a384a..6482c35 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -17,7 +17,6 @@ #include <cpu/x86/cache.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -314,13 +313,10 @@ /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | BIOS resource | - * | list (STM) | - * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE * | stacks | - * +-----------------+ <- .. - total_stack_size + * +-----------------+ <- smram + size - total_stack_size * | fxsave area | - * +-----------------+ <- .. - total_stack_size - fxsave_size + * +-----------------+ <- smram + size - total_stack_size - fxsave_size * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -362,10 +358,6 @@ /* Stacks start at the top of the region. */ base = smram; base += size; - - if (CONFIG(STM)) - base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; - params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index f6ab0bf..58d74c0 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -30,13 +30,14 @@ #if CONFIG(STM) void stm_update_smm_info( uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void stm_setup( + int cpu, uintptr_t perm_smbase, size_t perm_smsize, + uintptr_t staggered_smbase, size_t offset32); #else static inline void stm_update_smm_info(uintptr_t *, size_t *, size_t *) {} +static inline void stm_setup(int, uintptr_t, size_t, uintptr_t, size_t) {} #endif -void stm_setup( - uintptr_t mseg, int cpu, uintptr_t smbase, - uintptr_t smbase_base, uint32_t offset32); /* * Add resources in list to database. Allocate new memory areas as needed. diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index c389afa..c3c3ee8 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -154,10 +154,34 @@ static int stm_load_status = 0; +/* + * We cut off some space from the top of SMRAM and also increase + * the per CPU save-state for the TXT SMM descriptor: + * +--------------------+ <- smram + size + * | MSEG | + * +--------------------+ <- smram + size - MSEG size + * | BIOS Resource List | + * +--------------------+ <- smram + size - MSEG size - BIOS Resource list size + * | SMM module | + * | ... | + * | +-------------+ | + * | + + | + * | + ... + | + * | +-------------+ | + * | + TXT Desc. + | + * | + CPU 1 save + | + * | +-------------+ | + * | + TXT Desc. + | + * | + CPU 0 save + | + * | +-------------+ | + * +--------------------+ <- smram + */ void stm_update_smm_info( uintptr_t *const perm_smbase, size_t *const perm_smsize, size_t *const smm_save_state_size) { + *perm_smsize -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + *smm_save_state_size += sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); /* @@ -169,19 +193,22 @@ *smm_save_state_size = ALIGN_UP(*smm_save_state_size, 0x1000); } -void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, - uintptr_t base_smbase, uint32_t offset32) +void stm_setup( + const int cpu, const uintptr_t perm_smbase, const size_t perm_smsize, + const uintptr_t staggered_smbase, const size_t offset32) { msr_t InitMseg; msr_t MsegChk; uintptr_t addr_calc; // used to calculate the stm resource heap area + const uintptr_t mseg = perm_smbase + perm_smsize + CONFIG_BIOS_RESOURCE_LIST_SIZE; + printk(BIOS_DEBUG, "STM: set up for cpu %d\n", cpu); if (cpu == 0) { // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; + addr_calc = perm_smbase + perm_smsize; stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); @@ -204,7 +231,7 @@ cpu, MsegChk.hi, MsegChk.lo); // setup the descriptor for this cpu - setup_smm_descriptor((void *)smbase, (void *) base_smbase, + setup_smm_descriptor((void *)staggered_smbase, (void *)perm_smbase, cpu, offset32); } else { printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/c/coreboot/+/38769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5915ddeffdabe792b9c30cd72cc39a8f54ca6 Gerrit-Change-Number: 38769 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

3 6

[XS] Change in coreboot[master]: mb/google/brya/var/hades: Abort power on if any rails fail to come up
by Eric Lai (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eran Mitrani, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75534?usp=email ) Change subject: mb/google/brya/var/hades: Abort power on if any rails fail to come up ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Gerrit-Change-Number: 75534 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:09:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Unpack struct `_bios_directory_entry`
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41154 ) Change subject: amdfwtool: Unpack struct `_bios_directory_entry` ...................................................................... amdfwtool: Unpack struct `_bios_directory_entry` gcc (Debian 10-20200502-1) 10.0.1 20200502 (prerelease) [gcc-10 revision d128356d460:a9ed47dd155:0118d0397f94c307b76aa14abec99347a93da621] shows the warning below. /coreboot/util/amdfwtool/amdfwtool.c: In function 'integrate_bios_firmwares': /dev/shm/coreboot/util/amdfwtool/amdfwtool.c:964:7: warning: taking address of packed member of 'struct _bios_directory_entry' may result in an unaligned pointer value [-Waddress-of-packed-member] 964 | &biosdir->entries[count].source, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /coreboot/util/amdfwtool/amdfwtool.c:965:7: warning: taking address of packed member of 'struct _bios_directory_entry' may result in an unaligned pointer value [-Waddress-of-packed-member] 965 | &biosdir->entries[count].size)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Change-Id: I375ffec589cca8fe9d07dbe908c79348e863aa13 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/41154/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1ff86e6..c4acf81 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -484,7 +484,7 @@ uint32_t size; uint64_t source; uint64_t dest; -} __attribute__((packed)) bios_directory_entry; +} bios_directory_entry; typedef struct _bios_directory_table { bios_directory_hdr header; -- To view, visit https://review.coreboot.org/c/coreboot/+/41154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375ffec589cca8fe9d07dbe908c79348e863aa13 Gerrit-Change-Number: 41154 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: [UNTESTED] intel/stm: Drop now unneeded `num_cpus` param
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

3 3

Change in coreboot[master]: [UNTESTED] intel/stm: Place resource list right below MSEG
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

4 5

[S] Change in coreboot[master]: nb/intel/sandybridge/raminit: Add extended memtest
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22200?usp=email ) Change subject: nb/intel/sandybridge/raminit: Add extended memtest ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/22200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31bcf8348c97b9461ee0aa792b3e53c0225d7d48 Gerrit-Change-Number: 22200 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38163 ) Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ...................................................................... sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls Use code comments in the coreboot style and replace outb/inb.rdtsc calls to use coreboot provided functions. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 118 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/1 diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 9ddae38..ac52887 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -14,89 +14,98 @@ */ #include <amdblocks/acpimmio.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> #include <AGESA.h> -#include <amdlib.h> #include <northbridge/amd/agesa/dimmSpd.h> -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit; - address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */ - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */ - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error; @@ -127,15 +136,16 @@ return 0; } -static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); } int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); } diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8523db5..ac52887 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -14,90 +14,98 @@ */ #include <amdblocks/acpimmio.h> -#include <console/console.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> +#include <console/console.h> #include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/pi/dimmSpd.h> +#include <northbridge/amd/agesa/dimmSpd.h> -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit; - address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */ - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */ - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; } -/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error; @@ -128,15 +136,16 @@ return 0; } -static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); } int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 Gerrit-Change-Number: 38163 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023