coreboot-gerrit June 2023

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[S] Change in coreboot[master]: [TESTME] soc/intel/skylake: Define and use soc_get_rtc_failed()
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52467?usp=email ) Change subject: [TESTME] soc/intel/skylake: Define and use soc_get_rtc_failed() ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52467?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186d116cee14833ecd35b2907bbb3a95c9e9adf4 Gerrit-Change-Number: 52467 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: console/*: Use same indents for switch/case
by Felix Singer (Code Review) 10 Jun '23

10 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49204 ) Change subject: console/*: Use same indents for switch/case ...................................................................... console/*: Use same indents for switch/case Use same indents for switch/case to fix linter issues. Change-Id: I13c723c335d18bbdd2dcb041f44b187df6c5d728 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/console/vtxprintf.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49204/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index c7bb585..16044c3 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -127,12 +127,12 @@ repeat: ++fmt; /* this also skips first '%' */ switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; - } + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } /* get field width */ field_width = -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/49204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c723c335d18bbdd2dcb041f44b187df6c5d728 Gerrit-Change-Number: 49204 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/clevo/cml-u: Drop MAX_CPUS setting
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52608?usp=email ) Change subject: mb/clevo/cml-u: Drop MAX_CPUS setting ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3481e28b54ede77f5dac9eb74f74ae46004343e Gerrit-Change-Number: 52608 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/car/bootblock: Add post-console init callbacks
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36711 ) Change subject: soc/intel/car/bootblock: Add post-console init callbacks ...................................................................... soc/intel/car/bootblock: Add post-console init callbacks Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/bootblock.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36711/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5..063b444 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -35,8 +35,16 @@ bootblock_early_cpu_init(); } +void __weak bootblock_northbridge_init(void) { } +void __weak bootblock_southbridge_init(void) { } +void __weak bootblock_cpu_init(void) { } + void bootblock_soc_init(void) { /* Halt if there was a built in self test failure */ report_bist_failure(saved_bist); + /* Post console init */ + bootblock_northbridge_init(); + bootblock_southbridge_init(); + bootblock_cpu_init(); } diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h index 5adfd87..af9e45e 100644 --- a/src/cpu/intel/car/bootblock.h +++ b/src/cpu/intel/car/bootblock.h @@ -18,4 +18,8 @@ void bootblock_early_northbridge_init(void); void bootblock_early_southbridge_init(void); +void bootblock_northbridge_init(void); +void bootblock_southbridge_init(void); +void bootblock_cpu_init(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Gerrit-Change-Number: 36711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/x86/smm: Drop unnecessary loglevel check in module loader
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52429?usp=email ) Change subject: cpu/x86/smm: Drop unnecessary loglevel check in module loader ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dbdd2efabbe77a20bf447fdccfcad72534b941c Gerrit-Change-Number: 52429 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: [WIP] CONFIG(CHROMEOS_VPD_MISC)
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50878?usp=email ) Change subject: [WIP] CONFIG(CHROMEOS_VPD_MISC) ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I155dd4bfd78f9d062034c0a91608e012c97fbf2c Gerrit-Change-Number: 50878 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/prodrive/hermes: Send EOP at end of romstage
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52707?usp=email ) Change subject: mb/prodrive/hermes: Send EOP at end of romstage ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7312cda57e83d5acfeaaf1db4e788c913a6f62fb Gerrit-Change-Number: 52707 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: arch/x86/smbios: Validate data for type17
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44017 ) Change subject: arch/x86/smbios: Validate data for type17 ...................................................................... arch/x86/smbios: Validate data for type17 Validate that the memory frequency reported is within the spec. Helps identifying platforms where the unit is wrong (MT/s vs MHz). Change-Id: I8b3d51464a92ed25017127f911a2292b0e10fb04 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44017/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 700de23..f27006b 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1078,6 +1078,38 @@ return len; } +static void smbios_type17_validate_dimm(struct dimm_info *dimm) +{ + u16 minf, maxf; + + switch (dimm->ddr_type) { + case MEMORY_TYPE_DDR4: + minf = 800; maxf = 1600; + break; + case MEMORY_TYPE_LPDDR4: + minf = 1600; maxf = 2133; + break; + case MEMORY_TYPE_DDR3: + minf = 400; maxf = 1067; + break; + case MEMORY_TYPE_LPDDR3: + minf = 800; maxf = 1067; + break; + case MEMORY_TYPE_DDR2: + minf = 400; maxf = 534; + break; + case MEMORY_TYPE_LPDDR2: + minf = 400; maxf = 534; + break; + default: + printk(BIOS_ERR, "SMBIOS: Unknown DIMM type %x\n", dimm->ddr_type); + return; + } + + if (dimm->ddr_frequency < minf || dimm->ddr_frequency > maxf) + printk(BIOS_ERR, "SMBIOS: Type 17 has invalid memory frequency: %d MHz\n", dimm->ddr_frequency); +} + static int smbios_write_type17(unsigned long *current, int *handle) { int len = sizeof(struct smbios_type17); @@ -1094,6 +1126,7 @@ i++) { struct dimm_info *dimm; dimm = &meminfo->dimm[i]; + smbios_type17_validate_dimm(dimm); len = create_smbios_type17_for_dimm(dimm, current, handle); *current += len; totallen += len; -- To view, visit https://review.coreboot.org/c/coreboot/+/44017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3d51464a92ed25017127f911a2292b0e10fb04 Gerrit-Change-Number: 44017 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: smbios: Bump to 3.1
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44013 ) Change subject: smbios: Bump to 3.1 ...................................................................... smbios: Bump to 3.1 Set the entry point revision to the SMBIOS defined value and bump version to 3.1. All new fields introduced in 3.1 are already present and filled with valid data. Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index d7e8747..1f22076 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1374,7 +1374,7 @@ memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); se->major_version = 3; - se->minor_version = 0; + se->minor_version = 1; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1392,7 +1392,8 @@ memcpy(se3->anchor, "_SM3_", 5); se3->length = sizeof(struct smbios_entry30); se3->major_version = 3; - se3->minor_version = 0; + se3->minor_version = 1; + se3->entry_point_rev = 1; se3->struct_table_address = (u64)tables; se3->struct_table_length = len; -- To view, visit https://review.coreboot.org/c/coreboot/+/44013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930 Gerrit-Change-Number: 44013 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Bump to version 3.2
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44015 ) Change subject: arch/x86/smbios: Bump to version 3.2 ...................................................................... arch/x86/smbios: Bump to version 3.2 Add new fields for type 17 and fill it with valid data. Rename configured_clock_speed to configured_memory_speed in type 17. All other structs and enums are already up to date. Change-Id: Iae56ad6bcde76ed25dc678b7bfed3b330ceaa77e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/mainboard.c 5 files changed, 31 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44015/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index be51075..700de23 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -317,7 +317,7 @@ memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; /* Memory speed is in MT/s */ - t->configured_clock_speed = dimm->ddr_frequency * 2; + t->configured_memory_speed = dimm->ddr_frequency * 2; t->speed = dimm->ddr_frequency * 2; t->type = SMBIOS_MEMORY_DEVICE; @@ -366,6 +366,19 @@ /* no handle for error information */ t->memory_error_information_handle = 0xFFFE; t->attributes = dimm->rank_per_dimm; + + t->memory_technology = MEMORY_TECHNOLOGY_DRAM; + t->operating_mode_capability = MEMORY_OPERATING_MODE_CAP_UNKNOWN; + t->fw_version = smbios_add_string(t->eos, ""); + t->manufacturer_id = dimm->mod_id; + t->product_id = 0x0000; + t->sub_ctrl_manufacturer_id = 0x0000; + t->sub_ctrl_product_id = 0x0000; + t->non_volatile_size = ~0ULL; + t->volatile_size = ~0UL; + t->cache_size = ~0UL; + t->logical_size = ~0UL; + t->handle = *handle; *handle += 1; t->length = sizeof(struct smbios_type17) - 2; @@ -1376,7 +1389,7 @@ memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); se->major_version = 3; - se->minor_version = 1; + se->minor_version = 2; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1394,7 +1407,7 @@ memcpy(se3->anchor, "_SM3_", 5); se3->length = sizeof(struct smbios_entry30); se3->major_version = 3; - se3->minor_version = 1; + se3->minor_version = 2; se3->entry_point_rev = 1; se3->struct_table_address = (u64)tables; diff --git a/src/include/smbios.h b/src/include/smbios.h index cb354f7..aee81be 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -842,10 +842,21 @@ u8 part_number; u8 attributes; u32 extended_size; - u16 configured_clock_speed; + u16 configured_memory_speed; u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 operating_mode_capability; + u8 fw_version; + u16 manufacturer_id; + u16 product_id; + u16 sub_ctrl_manufacturer_id; + u16 sub_ctrl_product_id; + u64 non_volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 48f88d3..d7c96a4 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -197,7 +197,7 @@ t->memory_type = MEMORY_TYPE_DDR; t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; t->speed = 400; - t->configured_clock_speed = 400; + t->configured_memory_speed = 400; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); len = t->length + smbios_string_table_len(t->eos); *current += len; diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 3c7f2f7..0f5fce3 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -222,7 +222,7 @@ t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->configured_clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; + t->configured_memory_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 531fcd0..6326b97 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -208,7 +208,7 @@ agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->configured_clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; + t->configured_memory_speed = agesa_dmi->T17[0][0][0].ConfigSpeed * 2; t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; -- To view, visit https://review.coreboot.org/c/coreboot/+/44015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae56ad6bcde76ed25dc678b7bfed3b330ceaa77e Gerrit-Change-Number: 44015 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023