coreboot-gerrit June 2023

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[M] Change in coreboot[master]: lib/option: Move CMOS option backend to choice
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52856?usp=email ) Change subject: lib/option: Move CMOS option backend to choice ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcbc3db01d35b933678e5d6a203b2a9e406092fe Gerrit-Change-Number: 52856 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/clevo/n130wu: Remove host bridge from devicetree
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/53937?usp=email ) Change subject: mb/clevo/n130wu: Remove host bridge from devicetree ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/53937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44d5ee82ce8b8d5c092feca2562f763a3fbb3cae Gerrit-Change-Number: 53937 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Add MROM lock
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52556?usp=email ) Change subject: soc/intel/xeon_sp: Add MROM lock ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e13cd1478622e2d7e72eaa982190434645db2d Gerrit-Change-Number: 52556 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[XL] Change in coreboot[master]: lib: Upgrade LZMA Decoder to version 19.0
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41963?usp=email ) Change subject: lib: Upgrade LZMA Decoder to version 19.0 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/41963?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f43e8bdda6536c719879381cad6a921dd94718 Gerrit-Change-Number: 41963 Gerrit-PatchSet: 5 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: qma ster <qmastery16(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: post_code: replace die postcodes with die_with_post_code
by Sindhoor Tilak (Code Review) 10 Jun '23

10 Jun '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43131 ) Change subject: post_code: replace die postcodes with die_with_post_code ...................................................................... post_code: replace die postcodes with die_with_post_code This change replaces failure postcode calls with die_with_post_code calls Change-Id: I6188da11df046131eed1e77c41ae229852c2b5ac Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> --- M src/arch/x86/postcar_loader.c M src/drivers/intel/fsp1_1/fsp_util.c M src/lib/ramtest.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/xeon_sp/romstage.c 5 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43131/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index fd1c172..7b3088f 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -97,7 +97,8 @@ void prepare_and_run_postcar(struct postcar_frame *pcf) { if (postcar_frame_init(pcf, 0)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); fill_postcar_frame(pcf); diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d..a5ed5b2 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -123,8 +123,8 @@ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ - post_code(0x4F); - die("Can't find the FSP!\n"); + die_with_post_code(POST_FSP_FAILURE, + "Can't find the FSP!\n"); } } diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4..9b381f7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -108,7 +108,8 @@ } } if (failures) { - post_code(0xea); + die_with_post_code(POST_RAM_TEST_FAIL, + "\nDRAM did _NOT_ verify!\n"); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -126,7 +127,7 @@ */ printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); if (ram_bitset_nodie(start)) - die("DRAM ERROR"); + die_with_post_code(POST_RAM_FAILURE, "DRAM ERROR"); printk(BIOS_DEBUG, "Done.\n"); } @@ -198,8 +199,7 @@ write_phys(dst, backup); if (fail) { - post_code(0xea); - die("RAM INIT FAILURE!\n"); + die_with_post_code(POST_RAM_FAILURE, "RAM INIT FAILURE!\n"); } phys_memory_barrier(); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9fb80f8..991afc0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -120,9 +120,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 9f4d78d..2d1b02e 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -25,7 +25,8 @@ unlock_pam_regions(); if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); + die_with_post_code(POST_EXIT_CAR_INIT_FAIL, + "Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact -- To view, visit https://review.coreboot.org/c/coreboot/+/43131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6188da11df046131eed1e77c41ae229852c2b5ac Gerrit-Change-Number: 43131 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Advertise PM timer
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46848 ) Change subject: soc/intel/xeon_sp/cpx: Advertise PM timer ...................................................................... soc/intel/xeon_sp/cpx: Advertise PM timer Unclear why it was missing and if it's working. Test: Tianocore now boots. Change-Id: I7e68430c3e720561b85834c5f8c43c1c24da852f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46848/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 3066dda2..a4a3fc3 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -142,7 +142,7 @@ fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - + fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->pm1_evt_len = 4; @@ -169,6 +169,13 @@ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + /* * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. * The bit_width field intentionally overflows here. -- To view, visit https://review.coreboot.org/c/coreboot/+/46848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e68430c3e720561b85834c5f8c43c1c24da852f Gerrit-Change-Number: 46848 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable SATA ports
by Andrey Petrov (Code Review) 10 Jun '23

10 Jun '23

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39918 ) Change subject: soc/intel/xeon_sp/cpx: Enable SATA ports ...................................................................... soc/intel/xeon_sp/cpx: Enable SATA ports Looks like FSP does not explicity configure SATA ports as enabled. As result some payloads (SeaBIOS, TianoCore) can detect the drives but Linux kernel does not. Turns out the kernel does not touch disabled ports, while SeaBIOS just checks all available ports. Interestingly, SKX FSP seems to be enabling all the ports. This change hooks up some common SATA code which enables all ports. TEST=booted on Cedar Island CRB, make sure 7-pin SATA drive works Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39918/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 70703d0..2f637b1 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -17,6 +17,8 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select FSP_USES_CB_STACK + select SOC_INTEL_COMMON_BLOCK_SATA + select SOC_AHCI_PORT_IMPLEMENTED_INVERT config FSP_HEADER_PATH string "Location of FSP headers" -- To view, visit https://review.coreboot.org/c/coreboot/+/39918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 Gerrit-Change-Number: 39918 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48658 ) Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ...................................................................... soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM. Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address. Reserved 8 KiB as that seems to be the minimal common reserved size for the TPM MMIO area. Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/alderlake/espi.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 9 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/1 diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..f3c445a 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -27,6 +27,8 @@ */ static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ad9211b9..91b4b6e 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -9,7 +9,8 @@ #include "chip.h" static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = { - { 0xfed40000, 0x8000 }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0xfedc0000, 0x4000 }, { 0xfed20800, 16 }, { 0xfed20880, 8 }, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..b72c298 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -25,6 +25,8 @@ */ static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..1ecd929 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -23,6 +23,8 @@ */ static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..e4977be 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..3370999 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..7c80cbf 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -21,6 +21,8 @@ static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..d4ea81a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -30,6 +30,8 @@ */ static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..370a020 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -10,6 +10,8 @@ #include <chip.h> static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Gerrit-Change-Number: 48658 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Enable saving of MRC cache
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39440?usp=email ) Change subject: soc/intel/xeon_sp: Enable saving of MRC cache ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a655f3290bd203d621317bcab6fbf79e60790db Gerrit-Change-Number: 39440 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rocky Phagura Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: arch/riscv: Fix the method of detecting and removing mcause.interrupt
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/53945?usp=email ) Change subject: arch/riscv: Fix the method of detecting and removing mcause.interrupt ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/53945?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418 Gerrit-Change-Number: 53945 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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