coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/octopus: Enable Proximity Sensor
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25733?usp=email ) Change subject: mb/google/octopus: Enable Proximity Sensor ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/25733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8326aadab2c3c4042b8c859e637f279c39fd19db Gerrit-Change-Number: 25733 Gerrit-PatchSet: 2 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/hatch: Disable the eMMC controller for hatch
by V Sowmya (Code Review) 10 Jun '23

10 Jun '23

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615 Change subject: mb/google/hatch: Disable the eMMC controller for hatch ...................................................................... mb/google/hatch: Disable the eMMC controller for hatch eMMC controller is not used in hatch hence this patch adds the Kconfig option to disable the eMMC controller ACPI entries. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..15fe354 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select EXCLUDE_EMMC_INTERFACE if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/30615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Gerrit-Change-Number: 30615 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/hatch: Add SMI handlers
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30440?usp=email ) Change subject: mb/google/hatch: Add SMI handlers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Gerrit-Change-Number: 30440 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/hatch: Add SMI handlers
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30439?usp=email ) Change subject: mb/google/hatch: Add SMI handlers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Gerrit-Change-Number: 30439 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP
by Aamir Bohra (Code Review) 10 Jun '23

10 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30664 Change subject: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP ...................................................................... mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP **** DO NOT MERGE **** Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30664/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..4a47d12 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->RMT = 1; + memupd->FspmTestConfig.BdatEnable = 1; + mem_cfg->MrcFastBoot = 0; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + cannonlake_memcfg_init(mem_cfg, variant_memory_params(), &spd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Gerrit-Change-Number: 30664 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: sb/intel/spi: unify and refine VSCC handling
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28346?usp=email ) Change subject: sb/intel/spi: unify and refine VSCC handling ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27a9373f2402837682194e7097c6764851f1e5bd Gerrit-Change-Number: 28346 Gerrit-PatchSet: 23 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: lib/ext_stage_cache: Use uintptr_t * as argument
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36560 ) Change subject: lib/ext_stage_cache: Use uintptr_t * as argument ...................................................................... lib/ext_stage_cache: Use uintptr_t * as argument This avoids a cast. Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/tseg_region.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36560/1 diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index a8b8bb7..519db61 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -68,11 +68,11 @@ return 0; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3c7d9fa..9f70711 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -52,7 +52,7 @@ #endif /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 52c0d6f..f56a9a4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -31,12 +31,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, size + (uintptr_t)base); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); -- To view, visit https://review.coreboot.org/c/coreboot/+/36560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Gerrit-Change-Number: 36560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/intel/tigerlake_rvp: Configure eSPI IO decode range for EC
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36247?usp=email ) Change subject: mb/intel/tigerlake_rvp: Configure eSPI IO decode range for EC ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/36247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fc351aabd4f55489276a70292a4b78981f9e87 Gerrit-Change-Number: 36247 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/skylake: Improve comment for DISB
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36650 ) Change subject: soc/intel/skylake: Improve comment for DISB ...................................................................... soc/intel/skylake: Improve comment for DISB Either documentation or FSP is wrong, as the behaviour of DISB is actually reversed. Document that and warn about clearing the bit. Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/pmc.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36650/1 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ab9297f..3bc5c68 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -31,7 +31,16 @@ void pmc_set_disb(void) { - /* Set the DISB after DRAM init */ + /* + * Set the DISB after DRAM init. + * + * According to Document Number: 332691-002EN + * "Intel 100 Series and Intel C230 Series Chipset Family Platform + * Controller Hub (PCH) Vol2" this bit must be CLEARED after DRAM init. + * + * Tests showed that either documentation or FSP is wrong. Clearing this + * bit here causes full memory training on every boot. + */ u32 disb_val; #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_PMC; -- To view, visit https://review.coreboot.org/c/coreboot/+/36650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Gerrit-Change-Number: 36650 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: vendorcode/intel/fsp/tigerlake: Add tigerlake FSP header file template
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36243?usp=email ) Change subject: vendorcode/intel/fsp/tigerlake: Add tigerlake FSP header file template ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/36243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d064ea60e3b7c2d1114771b07cf7ec7f0e2b37 Gerrit-Change-Number: 36243 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: abandon

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coreboot-gerrit June 2023