coreboot-gerrit June 2023

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[M] Change in coreboot[master]: soc/intel/cmd/blk/cse: Cache ISH version in CMOS memory for cold boots
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75755?usp=email ) Change subject: soc/intel/cmd/blk/cse: Cache ISH version in CMOS memory for cold boots ...................................................................... soc/intel/cmd/blk/cse: Cache ISH version in CMOS memory for cold boots This patch stores the current ISH version in CMOS memory. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 69 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75755/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 925d2dc..3dc7b7d 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1172,54 +1172,6 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } -/* - * Helper function that stores current CSE firmware version to CBMEM memory, - * except during recovery mode. - */ -static void store_cse_rw_fw_version(void) -{ - if (vboot_recovery_mode_enabled()) - return; - - struct get_bp_info_rsp cse_bp_info; - if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) { - printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); - return; - } - size_t vers_size = sizeof(struct fw_version); - const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); - struct cse_fw_partition_info *cbmem_fw; - cbmem_fw = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*cbmem_fw)); - -#if CONFIG_SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS - struct fw_version prev_cse_fw_version; - get_cmos_cse_version(&prev_cse_fw_version); - - /* - * Compare if stored cse version (from the previous boot) is same as current - * running cse version. - */ - if (memcmp(&prev_cse_fw_version, &(cse_bp->fw_ver), vers_size)) { - /* write cse rw fw version to CMOS */ - set_cmos_cse_version(&(cse_bp->fw_ver)); - - /* write cse rw fw version to CBMEM */ - memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); - } else { - /* Current running CSE version is same as previous stored CSE version */ - if (memcmp(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size)) { - /* - * The CBMEM memory was reset during cold reboot, so the CSE version in - * CBMEM needs to be updated to the version stored in CMOS. - */ - memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); - } - } -#else - memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); -#endif -} - static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1285,43 +1237,90 @@ * This is because the command relies on resources that are not available * until DRAM initialization command has been sent. */ -static void store_ish_version(void) +static void store_ish_version(struct cse_fw_partition_info *cbmem_fw) { - if (!ENV_RAMSTAGE) + if (!CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) || + soc_is_ish_partition_enabled() == false) return; - if (vboot_recovery_mode_enabled()) + /* Get current ISH firmware version from CSE */ + struct fw_version_resp resp; + if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS + /* Update cmos stored ISH version with current version */ + set_cmos_ish_version(&(resp.manifest_data.version)); +#endif + /* Update cbmem stored ISH version with current version */ + memcpy(&(cbmem_fw->ish_partition_info.cur_ish_fw_version), + &(resp.manifest_data.version), sizeof(struct fw_version)); + } +} + +/* + * Helper function that stores current CSE firmware version to CBMEM memory, + * except during recovery mode. + */ +static void store_cse_rw_fw_version(void) +{ + if (!ENV_RAMSTAGE || vboot_recovery_mode_enabled()) return; - struct cse_fw_partition_info *version; - size_t size = sizeof(struct fw_version); - version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); - if (version == NULL) + struct get_bp_info_rsp cse_bp_info; + if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); return; + } + size_t vers_size = sizeof(struct fw_version); + const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); + struct cse_fw_partition_info *cbmem_fw; + cbmem_fw = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*cbmem_fw)); +#if CONFIG_SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS + struct fw_version prev_cse_fw_version; + get_cmos_cse_version(&prev_cse_fw_version); /* * Compare if stored cse version (from the previous boot) is same as current * running cse version. */ - if (memcmp(&version->ish_partition_info.prev_cse_fw_version, - &version->cur_cse_fw_version, sizeof(struct fw_version))) { + if (memcmp(&prev_cse_fw_version, &(cse_bp->fw_ver), vers_size)) { + /* write cse rw fw version to CMOS */ + set_cmos_cse_version(&(cse_bp->fw_ver)); + + /* write cse rw fw version to CBMEM */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); + store_ish_version(cbmem_fw); + } else { + /* Current running CSE version is same as previous stored CSE version */ + if (memcmp(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size)) { + /* + * The CBMEM memory was reset during cold reboot, so the firmware + * versions in CBMEM needs to be updated to the version stored in CMOS. + */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS + if(soc_is_ish_partition_enabled()) { + struct fw_version cmos_ish_version; + get_cmos_ish_version(&cmos_ish_version); + memcpy(&(cbmem_fw->ish_partition_info.cur_ish_fw_version), + &cmos_ish_version, vers_size); + } +#endif /* CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS */ + } + } +#else + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); + if (memcmp(&cbmem_fw->ish_partition_info.prev_cse_fw_version, + &cbmem_fw->cur_cse_fw_version, vers_size)) { /* * Current running CSE version is different than previous stored CSE version * which could be due to CSE update or rollback, hence, need to send ISHC * partition info cmd to know the currently running ISH version. */ - - struct fw_version_resp resp; - if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { - /* Update stored cse version with current version */ - memcpy(&(version->ish_partition_info.prev_cse_fw_version), - &(version->cur_cse_fw_version), size); - - /* Since cse version has been updated, ish version needs to be updated. */ - memcpy(&(version->ish_partition_info.cur_ish_fw_version), - &(resp.manifest_data.version), size); - } + store_ish_version(cbmem_fw); + memcpy(&(cbmem_fw->ish_partition_info.prev_cse_fw_version), + &cbmem_fw->cur_cse_fw_version, vers_size); } +#endif /* CONFIG_SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS */ } static void ramstage_cse_misc_ops(void *unused) @@ -1332,16 +1331,12 @@ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); - if (CONFIG(SOC_INTEL_STORE_CSE_VERSION)) - store_cse_rw_fw_version(); /* * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition * is available */ - if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && - soc_is_ish_partition_enabled()) { - store_ish_version(); - } + if (CONFIG(SOC_INTEL_STORE_CSE_VERSION)) + store_cse_rw_fw_version(); } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_misc_ops, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/75755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Gerrit-Change-Number: 75755 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Implement APIs to access ISH version in CMOS
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75754?usp=email ) Change subject: soc/intel/cmd/blk/cse: Implement APIs to access ISH version in CMOS ...................................................................... soc/intel/cmd/blk/cse: Implement APIs to access ISH version in CMOS This patch implements APIs to access ISH version in CMOS. The get API allows users to retrieve the current ISH version from CMOS memory. The set API allows users to set the ISH version in CMOS memory. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: If6472e5758e67c967158c4384c26142df46d9541 --- M src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/include/intelblocks/cse_cmos.h 2 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/75754/1 diff --git a/src/soc/intel/common/block/cse/cse_cmos.c b/src/soc/intel/common/block/cse/cse_cmos.c index be0455f..66a9659 100644 --- a/src/soc/intel/common/block/cse/cse_cmos.c +++ b/src/soc/intel/common/block/cse/cse_cmos.c @@ -23,10 +23,15 @@ #if CMOS_VSTART_partition_fw % 8 != 0 #error "The `partition firmware` CMOS entry needs to be byte aligned, check your cmos.layout." #endif // CMOS_VSTART_partition_fw % 8 != 0 - +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS +#if CMOS_VLEN_partition_fw != (24 * 8) +#error "The partition firmware entry needs to be 24 bytes long, check your cmos.layout." +#endif +#else #if CMOS_VLEN_partition_fw != (16 * 8) #error "The partition firmware entry needs to be 16 bytes long, check your cmos.layout." #endif +#endif # define PARTITION_FW_CMOS_OFFSET (CMOS_VSTART_partition_fw >> 3) @@ -41,6 +46,9 @@ struct cse_fw_table { uint32_t signature; struct fw_version cse_version; +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS + struct fw_version ish_version; +#endif uint16_t checksum; } __packed; @@ -122,3 +130,30 @@ memcpy(&version.cse_version, cse_version, sizeof(struct fw_version)); write_cmos_partition_version(&version); } + +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS +/* API that allows users to read ISH version stored in CMOS memory. */ +void get_cmos_ish_version(struct fw_version *ish_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* CMOS failed to read the ISH version. Possibly CMOS area has corrupted. */ + printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); + init_cmos_partition_version(&version); + } + memcpy(ish_version, &version.ish_version, sizeof(struct fw_version)); +} + +/* API that allows users to update ISH version stored in CMOS memory. */ +void set_cmos_ish_version(const struct fw_version *ish_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* CMOS failed to read the ISH version. Possibly CMOS area has corrupted. */ + printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); + init_cmos_partition_version(&version); + } + memcpy(&version.ish_version, ish_version, sizeof(struct fw_version)); + write_cmos_partition_version(&version); +} +#endif diff --git a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h index 8026a19..467b51c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h @@ -11,4 +11,11 @@ /* Function to update the cse version stored in CMOS memory */ void set_cmos_cse_version(const struct fw_version *cse_version); +#if CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS +/* Function to get the ish version stored in CMOS memory */ +void get_cmos_ish_version(struct fw_version *ish_version); +/* Function to update the ish version stored in CMOS memory */ +void set_cmos_ish_version(const struct fw_version *ish_version); +#endif /* CONFIG_SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS */ + #endif /* SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6472e5758e67c967158c4384c26142df46d9541 Gerrit-Change-Number: 75754 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/cmd/blk/cse: Add a config option to cache ISH version in CMOS
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75753?usp=email ) Change subject: soc/intel/cmd/blk/cse: Add a config option to cache ISH version in CMOS ...................................................................... soc/intel/cmd/blk/cse: Add a config option to cache ISH version in CMOS This patch adds a configuration option to store the ISH version in CMOS memory. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ic3b732545fb067638ba6e90d74cfdec1c9e1a1a4 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/75753/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index e411d33..1bceeba 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -61,6 +61,13 @@ help This configuration option stores CSE firmware version in CMOS memory. +config SOC_INTEL_CACHE_ISH_VERSION_IN_CMOS + bool + default y + depends on SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION && SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS + help + This configuration option stores CSE firmware version in CMOS memory. + config SOC_INTEL_STORE_CSE_VERSION bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/75753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3b732545fb067638ba6e90d74cfdec1c9e1a1a4 Gerrit-Change-Number: 75753 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75752?usp=email ) Change subject: soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots ...................................................................... soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots This patch stores the current CSE version in CMOS memory and update CBMEM version on cold boots. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I80ed134ba4d5434b977faec6d0c69aa103ac0267 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/75752/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1865c4f..925d2dc 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -9,6 +9,7 @@ #include <fmap.h> #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> +#include <intelblocks/cse_cmos.h> #include <intelblocks/cse_layout.h> #include <intelblocks/spi.h> #include <security/vboot/misc.h> @@ -1185,10 +1186,38 @@ printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); return; } + size_t vers_size = sizeof(struct fw_version); const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); - struct cse_fw_partition_info *version; - version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); - memcpy(&(version->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); + struct cse_fw_partition_info *cbmem_fw; + cbmem_fw = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*cbmem_fw)); + +#if CONFIG_SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS + struct fw_version prev_cse_fw_version; + get_cmos_cse_version(&prev_cse_fw_version); + + /* + * Compare if stored cse version (from the previous boot) is same as current + * running cse version. + */ + if (memcmp(&prev_cse_fw_version, &(cse_bp->fw_ver), vers_size)) { + /* write cse rw fw version to CMOS */ + set_cmos_cse_version(&(cse_bp->fw_ver)); + + /* write cse rw fw version to CBMEM */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); + } else { + /* Current running CSE version is same as previous stored CSE version */ + if (memcmp(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size)) { + /* + * The CBMEM memory was reset during cold reboot, so the CSE version in + * CBMEM needs to be updated to the version stored in CMOS. + */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); + } + } +#else + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size); +#endif } static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, -- To view, visit https://review.coreboot.org/c/coreboot/+/75752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80ed134ba4d5434b977faec6d0c69aa103ac0267 Gerrit-Change-Number: 75752 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmd/blk/cse: Implement APIs to access CSE version in CMOS
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75751?usp=email ) Change subject: soc/intel/cmd/blk/cse: Implement APIs to access CSE version in CMOS ...................................................................... soc/intel/cmd/blk/cse: Implement APIs to access CSE version in CMOS This patch implements APIs to access the CSE version in CMOS. The get API allows users to retrieve the current CSE version from CMOS memory. The set API allows users to set the CSE version in CMOS memory. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I3d5d895ab00766e0f1964d06e58738a2addb911f --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_cmos.c A src/soc/intel/common/block/include/intelblocks/cse_cmos.h 3 files changed, 139 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/75751/1 diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 3e11279..ccf2f6e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,4 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS) += cse_cmos.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c diff --git a/src/soc/intel/common/block/cse/cse_cmos.c b/src/soc/intel/common/block/cse/cse_cmos.c new file mode 100644 index 0000000..be0455f --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_cmos.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cse_cmos.h> +#include <ip_checksum.h> +#include <pc80/mc146818rtc.h> + +#define PARTITION_FW_SIGNATURE 0x46575054 /* 'FWPT' */ + +/* + * We need a region in CMOS to store the firmware versions. + * + * This can either be declared as part of the option + * table or statically defined in the board config. + */ +#if CONFIG(USE_OPTION_TABLE) +# include "option_table.h" + +#ifndef CMOS_VSTART_partition_fw +#error "The `ramtop` CMOS entry is missing, please add it to your cmos.layout." +#endif + +#if CMOS_VSTART_partition_fw % 8 != 0 +#error "The `partition firmware` CMOS entry needs to be byte aligned, check your cmos.layout." +#endif // CMOS_VSTART_partition_fw % 8 != 0 + +#if CMOS_VLEN_partition_fw != (16 * 8) +#error "The partition firmware entry needs to be 16 bytes long, check your cmos.layout." +#endif + +# define PARTITION_FW_CMOS_OFFSET (CMOS_VSTART_partition_fw >> 3) + +#else +# if (CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET != 0) +# define PARTITION_FW_CMOS_OFFSET CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET +# else +# error "Must configure CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET" +# endif +#endif + +struct cse_fw_table { + uint32_t signature; + struct fw_version cse_version; + uint16_t checksum; +} __packed; + +/* Helper function to read firmware version from cmos memory. */ +static uint32_t read_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + u16 csum; + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + *p = cmos_read(offset + i); + + /* Verify signature */ + if (version->signature != PARTITION_FW_SIGNATURE) { + printk(BIOS_DEBUG, "cse firmware partition invalid signature\n"); + return -1; + } + + /* Verify checksum over signature and firmware versions only */ + csum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + if (csum != version->checksum) { + printk(BIOS_DEBUG, "cse firmware partition checksum mismatch\n"); + return -1; + } + + return 0; +} + +/* Helper function to write firmware version to cmos memory. */ +static void write_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + + /* Checksum over signature and firmware versions only */ + version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + cmos_write(*p, offset + i); +} + +/* Helper function to initialize cmos firmware version. */ +static void init_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + version->signature = PARTITION_FW_SIGNATURE; + memset(&version->cse_version, 0, sizeof(struct fw_version)); + version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + cmos_write(*p, offset + i); +} + +/* API that allows users to read CSE version stored in CMOS memory. */ +void get_cmos_cse_version(struct fw_version *cse_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(cse_version, &version.cse_version, sizeof(struct fw_version)); +} + +/* API that allows users to update CSE version stored in CMOS memory. */ +void set_cmos_cse_version(const struct fw_version *cse_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(&version.cse_version, cse_version, sizeof(struct fw_version)); + write_cmos_partition_version(&version); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h new file mode 100644 index 0000000..8026a19 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H +#define SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H + +#include <intelblocks/cse.h> + +/* Function to get the cse version stored in CMOS memory */ +void get_cmos_cse_version(struct fw_version *cse_version); + +/* Function to update the cse version stored in CMOS memory */ +void set_cmos_cse_version(const struct fw_version *cse_version); + +#endif /* SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5d895ab00766e0f1964d06e58738a2addb911f Gerrit-Change-Number: 75751 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75750?usp=email ) Change subject: soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS ...................................................................... soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS This patch adds a configuration option to store the CSE version in CMOS memory. It also includes another configuration option to fix the CMOS offset for the CSE version. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I799f100ed4d319d93b06c68267fd2b03f2f5e7de --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/75750/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 54fd27c..e411d33 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,22 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_PARTITION_FW_CMOS_OFFSET + int + default 72 + depends on SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS + help + This configuration option stores the starting offset of firmware partition versions in + CMOS memory. The offset should be byte aligned and must leave enough memory to store + required firmware partition versions. + +config SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS + bool + default y + depends on SOC_INTEL_STORE_CSE_VERSION + help + This configuration option stores CSE firmware version in CMOS memory. + config SOC_INTEL_STORE_CSE_VERSION bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/75750?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799f100ed4d319d93b06c68267fd2b03f2f5e7de Gerrit-Change-Number: 75750 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Hook get CSE version into `.final`
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email ) Change subject: soc/intel/cmd/blk/cse: Hook get CSE version into `.final` ...................................................................... soc/intel/cmd/blk/cse: Hook get CSE version into `.final` This patch calls get ISH version function from .final hook if platform has required config (`SOC_INTEL_STORE_CSE_VERSION`) support. BUG=b:280722061 TEST=The CSE version, 16.50.0.1232, was retrieved on nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/75749/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 990e106..7d3ac29 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1418,12 +1418,28 @@ cse_final_end_of_firmware(); } +static void intel_cse_get_version(void) +{ + struct cse_fw_partition_info *version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); + if (version == NULL) + return; + + printk(BIOS_DEBUG, "CSE version: %d.%d.%d.%d\n", + version->cur_cse_fw_version.major, + version->cur_cse_fw_version.minor, + version->cur_cse_fw_version.hotfix, + version->cur_cse_fw_version.build); +} + /* * `cse_final` function is native implementation of equivalent events performed by - * each FSP NotifyPhase() API invocations. + * each FSP NotifyPhase() API invocations. It also displays CSE firmware version + * if stored in CBMEM memory. */ static void cse_final(struct device *dev) { + if (CONFIG(SOC_INTEL_STORE_CSE_VERSION)) + intel_cse_get_version(); /* * SoC user can have two options for sending EOP: * 1. Choose to send EOP late -- To view, visit https://review.coreboot.org/c/coreboot/+/75749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Gerrit-Change-Number: 75749 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/cmd/blk/cse: Perform cse version store under pertinent option
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75748?usp=email ) Change subject: soc/intel/cmd/blk/cse: Perform cse version store under pertinent option ...................................................................... soc/intel/cmd/blk/cse: Perform cse version store under pertinent option This patch ensures that the CSE version store will be performed when the SOC_INTEL_STORE_CSE_VERSION configuration option is set. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Iebe27d3277bb6343cc818069bcbb2dc2e8ef0413 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/75748/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 733f68b..1865c4f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1303,13 +1303,14 @@ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); + if (CONFIG(SOC_INTEL_STORE_CSE_VERSION)) + store_cse_rw_fw_version(); /* * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition * is available */ if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && soc_is_ish_partition_enabled()) { - store_cse_rw_fw_version(); store_ish_version(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe27d3277bb6343cc818069bcbb2dc2e8ef0413 Gerrit-Change-Number: 75748 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mainboard/google/brya: Enable CSE version store for nissa
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Tarun Tuli. Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75747?usp=email ) Change subject: mainboard/google/brya: Enable CSE version store for nissa ...................................................................... mainboard/google/brya: Enable CSE version store for nissa This patch enables the storage of the CSE version in the CBMEM memory for the nissa board. It also specifies that the CSE version must be stored before other firmware partition versions. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I8ffee751f29af5b34e3383b0053e1267e496e74d --- M src/mainboard/google/brya/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/75747/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b27945e..c7d7c5b 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -87,7 +87,8 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + select SOC_INTEL_STORE_CSE_VERSION + select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION if SOC_INTEL_STORE_CSE_VERSION select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE -- To view, visit https://review.coreboot.org/c/coreboot/+/75747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ffee751f29af5b34e3383b0053e1267e496e74d Gerrit-Change-Number: 75747 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version
by Dinesh Gehlot (Code Review) 10 Jun '23

10 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75746?usp=email ) Change subject: soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version ...................................................................... soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version This patch implements a new kconfig option, that will store CSE version in CBMEM memory when enabled. BUG=b:280722061 Test=Verified the changes nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: If8a62d00e6ed15fbe595f3729d921df8cef42fdb --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/75746/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 26c623f..54fd27c 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,13 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_STORE_CSE_VERSION + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + This configuration option stores CSE firmware version in CBMEM memory. + config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/75746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8a62d00e6ed15fbe595f3729d921df8cef42fdb Gerrit-Change-Number: 75746 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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