coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[master]: smm: Invalid the smm handler region instead of the whole
by Arthur Heymans (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69783?usp=email ) Change subject: smm: Invalid the smm handler region instead of the whole ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/cpu/smm/smm_relocate.c: https://review.coreboot.org/c/coreboot/+/69783/comment/d0d95242_4b7af00f : PS4, Line 85: tseg_valid(); : lock_smm(); > https://review.coreboot.org/c/coreboot/+/64871/comments/42ed8bbb_f4efd5eb I'm a bit confused. amds3laterestore() is called before the CPU init so how is it affected? -- To view, visit https://review.coreboot.org/c/coreboot/+/69783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cd422f35b3dfa25ae8ed8034f05f8d47350fd6e Gerrit-Change-Number: 69783 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 21:17:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75768?usp=email ) Change subject: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn ...................................................................... soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn This patch renames `cse_store_rw_fw_version` function that store currently running CSE RW FW version inside CBMEM. Additionally, perform the CSE RW FW storing operation unconditionally. TEST=Able to build and boot google/marasov. Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/75768/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 7063ecb..97f114c 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1175,7 +1175,7 @@ * Helper function that stores current CSE firmware version to CBMEM memory, * except during recovery mode. */ -static void store_cse_rw_fw_version(void) +static void cse_store_rw_fw_version(void) { if (vboot_recovery_mode_enabled()) return; @@ -1303,15 +1303,15 @@ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); + /* Store the CSE RW Firmware Version into CBMEM */ + cse_store_rw_fw_version(); /* - * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition + * Store the ISH RW Firmware Version into CBMEM if ISH partition * is available */ if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) && - soc_is_ish_partition_enabled()) { - store_cse_rw_fw_version(); + soc_is_ish_partition_enabled()) store_ish_version(); - } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_misc_ops, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/75768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Gerrit-Change-Number: 75768 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Tarun Tuli. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75767?usp=email ) Change subject: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config ...................................................................... {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/ish/ish.c M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/chip.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 6 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/75767/1 diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 0415af0..a84be5b 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -63,7 +63,7 @@ static void intel_ish_final(struct device *dev) { - if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)) intel_ish_get_version(); } diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b27945e..2a9941a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -87,7 +87,7 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + select SOC_INTEL_STORE_ISH_FW_VERSION select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index f052279..7f24032 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -162,7 +162,7 @@ } #endif -#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) /* * SoC override API to identify if ISH Firmware existed inside CSE FPT. * diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 26c623f..d809e03 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,22 +45,23 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. -config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION +config SOC_INTEL_STORE_ISH_FW_VERSION bool default n depends on DRIVERS_INTEL_ISH help - This configuration option stores CSE FPT partitions' version in CBMEM memory. - This information can be used to identify the currently running firmware partition + This configuration option stores ISH version in CBMEM area. + This information can be used to identify the currently running ISH firmware version. - The cost of sending HECI command to read the CSE FPT is significant (~200ms) - hence, the idea is to read the CSE RW version on every cold reset (to cover - the CSE update scenarios) and store into CBMEM to avoid the cost of resending - the HECI command in all consecutive warm boots. + ISH BUP is sitting inside the CSE firmware partition. The way to retrieve the + ISH version is by sending the HECI command to read the CSE FPT. The cost of sending + HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to + read the CSE RW version on every cold reset (to cover the CSE update scenarios) + and store into CBMEM to avoid the cost of resending the HECI command in all + consecutive warm boots. - Later boot stages can just read the CBMEM ID to retrieve the ISH version if - required. + Later boot stages can just read the CBMEM ID to retrieve the ISH version. Additionally, ensure this feature is platform specific hence, only enabled for the platform that would like to store the ISH version into the CBMEM and diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 733f68b..7063ecb 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1307,7 +1307,7 @@ * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition * is available */ - if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && + if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) && soc_is_ish_partition_enabled()) { store_cse_rw_fw_version(); store_ish_version(); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 23a4490..636b1f4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -528,7 +528,7 @@ * identifying the UFS enabled device is enough to conclude if ISH partition is * available. */ -#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) bool soc_is_ish_partition_enabled(void); #else static inline bool soc_is_ish_partition_enabled(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/75767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Gerrit-Change-Number: 75767 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik. Subrata Banik has uploaded a new patch set (#2) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` ...................................................................... soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Version:" [DEBUG] CSE version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/75749/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Gerrit-Change-Number: 75749 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Set FVM configuration for MTL-P 28W
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Herrmann, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75764?usp=email ) Change subject: mb/google/rex: Set FVM configuration for MTL-P 28W ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75764/comment/cbf1d975_80e51cc8 : PS1, Line 60: register "cep_enable[VR_DOMAIN_IA]" = "1" > Acknowledged Current Excursion Protection (CEP) is a Processor integrated detector which senses when the Processor load current exceeds a preset threshold by monitoring for a Processor power domain voltage droop at the Processor power domain IMVP VR sense point. -- To view, visit https://review.coreboot.org/c/coreboot/+/75764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If834c1af8141a19fd2daae653579225b77cfa6c8 Gerrit-Change-Number: 75764 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 21:01:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Set FVM configuration for MTL-P 28W
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Herrmann, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75764?usp=email ) Change subject: mb/google/rex: Set FVM configuration for MTL-P 28W ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75764/comment/62a79533_a25adb52 : PS1, Line 60: register "cep_enable[VR_DOMAIN_IA]" = "1" > > what is cep enable? […] Acknowledged https://review.coreboot.org/c/coreboot/+/75764/comment/663e6e50_63452992 : PS1, Line 61: register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "372" # 93A > > I think these are out of date. The document I have is 91A, 54A, and 27A respectively. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If834c1af8141a19fd2daae653579225b77cfa6c8 Gerrit-Change-Number: 75764 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 20:36:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: smm: Invalid the smm handler region instead of the whole
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Bao Zheng, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69783?usp=email ) Change subject: smm: Invalid the smm handler region instead of the whole ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/cpu/smm/smm_relocate.c: https://review.coreboot.org/c/coreboot/+/69783/comment/70577ffe_032c0774 : PS4, Line 85: tseg_valid(); : lock_smm(); > Maybe you want to move this later in the bootprocess? https://review.coreboot.org/c/coreboot/+/64871/comments/42ed8bbb_f4efd5eb -- To view, visit https://review.coreboot.org/c/coreboot/+/69783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cd422f35b3dfa25ae8ed8034f05f8d47350fd6e Gerrit-Change-Number: 69783 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 20:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
by Jason Glenesk (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Jason Nien, Karthik Ramasubramanian, Matt DeVillier, Paul Menzel. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75698?usp=email ) Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75698?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Gerrit-Change-Number: 75698 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 19:53:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: lib/coreboot_table.c: Add a pointer to SMBIOS in coreboot tables
by Julius Werner (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, David Milosevic, Maximilian Brune. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75765?usp=email ) Change subject: lib/coreboot_table.c: Add a pointer to SMBIOS in coreboot tables ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can't you just use the lb_cbmem_entry tag for CBMEM_ID_SMBIOS instead? We've been trying to deprecate individual coreboot table entries for memory regions because we already have the generic CBMEM records for all CBMEM areas anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/75765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796dd426feefb0785c0222fb4fc34dae7b70982c Gerrit-Change-Number: 75765 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 19:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Add amdfw.cfg
by Matt DeVillier (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Jason Nien, Jon Murphy, Karthik Ramasubramanian, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75694?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add amdfw.cfg ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: we have a better long-term solution ready, there's no need for a variant-specific ABL in upstream or ToT -- To view, visit https://review.coreboot.org/c/coreboot/+/75694?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9237c5dddda25da84e2578495a3b5ed7983d6e63 Gerrit-Change-Number: 75694 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 19:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023