coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by Reka Norman (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: ChiaLing, Ryan Lin, Zhuohao Lee. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75678?usp=email ) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/power_limit.h: https://review.coreboot.org/c/coreboot/+/75678/comment/41f5858e_8d1ab4fd : PS2, Line 39: /* Minimum ROP */ : uint16_t min_rop; > This is not related to PsysPl1. Please move it to the CL where it's used. Actually, let's get rid of the min_rop calculation for now. We can leave pl4 at the default of 60W for now and discuss more in the bug about how to set it. -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 00:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75745?usp=email ) Change subject: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/osiris/memory/Makefile.inc M src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: Derek Huang: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Ren Kuo: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Tyler Wang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc index eb91988..3a011cf 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt index 11359505..6d2a335 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H54G56CYRBX247 1 (0001) K4U6E3S4AB-MGCL 0 (0000) K4UBE3D4AB-MGCL 1 (0001) +MT53E2G32D4NQ-046 WT:C 2 (0010) diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt index a188982..eab1b17 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C -- To view, visit https://review.coreboot.org/c/coreboot/+/75745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Gerrit-Change-Number: 75745 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/rex: change ramstage compression to LZ4
by Wonkyu Kim (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75769?usp=email to look at the new patch set (#2). Change subject: mb/google/rex: change ramstage compression to LZ4 ...................................................................... mb/google/rex: change ramstage compression to LZ4 for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms(30-37ms) while SPI size impact is 230KB. For detail, refer below. Exising: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact( 73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded --- M src/mainboard/google/rex/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/75769/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: mb/google/rex: change ramstage compression to LZ4
by Wonkyu Kim (Code Review) 12 Jun '23

12 Jun '23

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: change ramstage compression to LZ4 ...................................................................... mb/google/rex: change ramstage compression to LZ4 for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms(30-37ms) while SPI size imact is 230KB. For detail, refer below. Exising: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact( 73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded --- M src/mainboard/google/rex/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/75769/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 0fb4176..0b0f395 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -23,6 +23,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_DISABLE_STAGE_CACHE select MAINBOARD_HAS_TPM2 + select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by Reka Norman (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: ChiaLing, Ryan Lin, Zhuohao Lee. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75678?usp=email ) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75678/comment/6b41c7d2_45558e78 : PS2, Line 10: More power : budget for SOC may be released accordingly. This is not true, as discussed in the bug. File src/soc/intel/common/block/include/intelblocks/power_limit.h: https://review.coreboot.org/c/coreboot/+/75678/comment/8f13b50f_c250dd06 : PS2, Line 39: /* Minimum ROP */ : uint16_t min_rop; This is not related to PsysPl1. Please move it to the CL where it's used. -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 23:57:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: cbfs: Allow controlling decompression of unverified files
by Julius Werner (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Angel Pons, Benjamin Doron, Jakub Czapiga, Maximilian Brune, Paul Menzel, Subrata Banik, Yu-Ping Wu. Hello Angel Pons, Benjamin Doron, Jakub Czapiga, Maximilian Brune, Paul Menzel, Subrata Banik, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75457?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Jakub Czapiga, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: cbfs: Allow controlling decompression of unverified files ...................................................................... cbfs: Allow controlling decompression of unverified files This patch adds a new Kconfig that controls whether CBFS APIs for unverified areas will allow file decompression when CBFS verification is enabled. This should be disallowed by default because it exposes the attack surface of all supported decompression algorithms. Make allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_ COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b --- M src/lib/Kconfig.cbfs_verification M src/lib/cbfs.c M src/soc/intel/common/block/cse/Kconfig 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/75457/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b Gerrit-Change-Number: 75457 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM
by Fred Reitberger (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Martin Roth, Paul Menzel. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74970?usp=email ) Change subject: mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74970/comment/2a225c8c_0e4f882c : PS1, Line 10: > Fred, you wrote you set it WIP while this is investigated. […] I have not found the cause yet. Once the root cause has been found and fixed, this patch will likely be reverted but until then the reduction in kernel error logs is quite significant and aids in debugging other issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/74970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290 Gerrit-Change-Number: 74970 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 22:20:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM
by Paul Menzel (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74970?usp=email ) Change subject: mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74970/comment/7a3f5bef_35991e5c : PS1, Line 10: > No, it's not documented, and won't be. […] Fred, you wrote you set it WIP while this is investigated. Did you find the cause? -- To view, visit https://review.coreboot.org/c/coreboot/+/74970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290 Gerrit-Change-Number: 74970 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 21:54:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: drivers/wwan/fm: Fix format string vulnerability with snprintf
by Cliff Huang (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Hannah Williams, Jamie Ryu, Paul Menzel, Tarun Tuli, Wonkyu Kim. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75733?usp=email ) Change subject: drivers/wwan/fm: Fix format string vulnerability with snprintf ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6b7d70c0b2b86d0918e58348dccd206a7ee9193 Gerrit-Change-Number: 75733 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 12 Jun 2023 21:32:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Set FVM configuration for MTL-U 15W
by Paul Menzel (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75763?usp=email ) Change subject: mb/google/rex: Set FVM configuration for MTL-U 15W ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75763/comment/6f0792c6_a535045e : PS3, Line 7: Set FVM configuration for MTL-U 15W Maybe: > Enable Fast V-Mode for MTL-U 15W https://review.coreboot.org/c/coreboot/+/75763/comment/54617e02_6845569a : PS3, Line 9: FVM Probably the doc says it, but maybe add a small sentence, what benefit the doc states about enabling the mode. File src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75763/comment/19860b7d_1ca12b80 : PS3, Line 71: A a -- To view, visit https://review.coreboot.org/c/coreboot/+/75763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05 Gerrit-Change-Number: 75763 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 21:21:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023