coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by ChiaLing (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: ChiaLing, Paul Menzel, Ryan Lin, Subrata Banik, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Subrata Banik, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75679?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... soc/intel/jasperlake: Add per-SKU power limits Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/blipper/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/haboki/overridetree.cb M src/mainboard/google/dedede/variants/kracko/overridetree.cb M src/mainboard/google/dedede/variants/lalala/overridetree.cb M src/mainboard/google/dedede/variants/lantis/overridetree.cb M src/mainboard/google/dedede/variants/madoo/overridetree.cb M src/mainboard/google/dedede/variants/magolor/overridetree.cb M src/mainboard/google/dedede/variants/metaknight/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/shotzo/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/systemagent.c 16 files changed, 206 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/75679/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 6 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Paul Menzel, TangYiwei, Tim Chu, Ziang Wang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 03:09:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by ChiaLing (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: ChiaLing, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75678?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... soc/intel/common: Add PsysPl1 support Set PsysPL1 in set_power_limits in order to increase system performance for no battery design. BUG=b:281479111 TEST=emerge-dedede coreboot and check PsysPl1 value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75678/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by ChiaLing (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: ChiaLing, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75678?usp=email to look at the new patch set (#3). Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... soc/intel/common: Add PsysPl1 support Set PsysPL1 in set_power_limits in order to increase system performance for no battery design. BUG=b:281479111 TEST=emerge-dedede coreboot and check PsysPl1 value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75678/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 3 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 7: (3 comments) Patchset: PS5: > Should change the wording and format hmm. Done File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/a0a4b75b_fb488ca9 : PS5, Line 263: if (code >= 0x01 && code <= 0x23) : return type[code - 0x01]; : return "Unsupported memory type"; > I don't expect the old project want to select this config, we can save some static memories :p Done https://review.coreboot.org/c/coreboot/+/75756/comment/f61717bd_dec7ced8 : PS5, Line 1046: > b/c this would need check many things if empty slot. so I add in create_smbios_type17_for_dimm. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 7 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 13 Jun 2023 02:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Subrata Banik, Tarun Tuli. Hello Paul Menzel, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75756?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... arch/x86: Introduce DUMP_SMBIOS_TYPE17 config DDR5 spd is not supported read by coreboot. But FSP can read it, so print the memory information from smbios type17 dimm information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 --- M src/arch/x86/Kconfig M src/arch/x86/smbios.c 2 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/75756/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 7 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Ziang Wang (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Paul Menzel, TangYiwei, Tim Chu. Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Just noticed there is a more advanced (code-wise but not wrt. the commit message) […] Thanks for pointing out, looks like in PR:69500 some extra changes getting rid of void pointers have been added, but IMHO it is not necessary because void* pointers are basically everywhere in ACPI/SMBIOS... I mean, maybe the void*-pointer-not-portable issue is out of the scope of this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 02:45:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Annie Chen (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, David Hendricks, Felix Singer, Hung-Wei Chen, Jonathan Zhang, Lean Sheng Tan, Paul Menzel. Annie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email ) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75598/comment/b433e0ac_9ca8392b : PS2, Line 13: 1Gbase-T > Please add a space after 1. Done Patchset: PS1: > Please look at commit 30e743e7cc7f (mb/ibm: Add 4 SPR sockets server board IBM SBP1), Ie21c744224e8d […] Done Patchset: PS5: > I sent a message to the mailing list [1] before seeing this comment. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 6 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 02:44:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Annie Chen (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, David Hendricks, Felix Singer, Hung-Wei Chen, Jonathan Zhang, Lean Sheng Tan, Paul Menzel. Hello Angel Pons, Arthur Heymans, David Hendricks, Hung-Wei Chen, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75598?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Hung-Wei Chen, Code-Review+1 by Jonathan Zhang, Verified+1 by build bot (Jenkins) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... mb/inventec: Add Intel SPR server board Inventec Transformers CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen <Chen.AnnieET(a)inventec.com> --- A configs/builder/config.transformers A src/mainboard/inventec/Kconfig A src/mainboard/inventec/Kconfig.name A src/mainboard/inventec/transformers/Kconfig A src/mainboard/inventec/transformers/Kconfig.name A src/mainboard/inventec/transformers/Makefile.inc A src/mainboard/inventec/transformers/acpi/platform.asl A src/mainboard/inventec/transformers/board.fmd A src/mainboard/inventec/transformers/board_info.txt A src/mainboard/inventec/transformers/bootblock.c A src/mainboard/inventec/transformers/devicetree.cb A src/mainboard/inventec/transformers/dsdt.asl A src/mainboard/inventec/transformers/include/mainboard_ras.h A src/mainboard/inventec/transformers/include/sprsp_ac_iio.h A src/mainboard/inventec/transformers/include/sprsp_gpio.h A src/mainboard/inventec/transformers/ipmi.c A src/mainboard/inventec/transformers/ipmi.h A src/mainboard/inventec/transformers/ramstage.c A src/mainboard/inventec/transformers/romstage.c 19 files changed, 937 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75598/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 6 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel: Add max memory speed into dimm info
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75810?usp=email ) Change subject: soc/intel: Add max memory speed into dimm info ...................................................................... soc/intel: Add max memory speed into dimm info Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check coreboot log can dump the max speed. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 13 files changed, 29 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/75810/1 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 740a4a2..dfe3b32 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -140,7 +140,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 9432011..3bcb7bb 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -83,6 +83,7 @@ 0, src_dimm->MfgId, 0, + 0, 0); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 9922b28..fe1b3b3 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -89,7 +89,8 @@ 0, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a417359..c16405c 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -108,7 +108,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 5ab2dbc..818a35e 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -14,13 +14,17 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id) + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency) { dimm->mod_id = mod_id; dimm->mod_type = mod_type; dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; + /* keep ddr_frequency for backward compatible */ dimm->ddr_frequency = frequency; + dimm->configured_speed_mts = frequency; + dimm->max_speed_mts = max_frequency; dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 410b2fd..9fb42b5 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -14,6 +14,7 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id); + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 427cee5..3dfb7c2 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 9cec859..3688f9e 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index b5351de..3df480c 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -108,7 +108,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 02ae19a..01ee804 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -112,7 +112,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index c1aca17..31b19d2 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 265ab70..fe2ca86 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -81,9 +81,6 @@ return; } dest_dimm = &mem_info->dimm[index]; - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; dimm_info_fill(dest_dimm, src_dimm.DimmSize << 6, 0x1a, /* hard-coded memory device type as DDR4 */ @@ -99,7 +96,8 @@ true, /* hard-coded as ECC supported */ src_dimm.VendorID, src_dimm.actKeyByte2, - 0); + 0, + get_max_memory_speed(src_dimm.commonTck)); index++; num_dimms++; } else if (mainboard_dimm_slot_exists(0, ch, dimm)) { diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index fef4d94..8004730 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -304,9 +304,7 @@ the board. */ continue; } - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; + dest_dimm->soc_num = soc; if (hob->DramType == SPD_TYPE_DDR5) { @@ -328,7 +326,8 @@ sizeof(src_dimm.PartNumber), (const uint8_t *)&src_dimm.serialNumber[0], data_width, vdd_voltage, true, /* hard-coded as ECC supported */ - src_dimm.VendorID, src_dimm.actKeyByte2, 0); + src_dimm.VendorID, src_dimm.actKeyByte2, 0, + get_max_memory_speed(src_dimm.commonTck)); dimm_num++; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Gerrit-Change-Number: 75810 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023