coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[XS] Change in coreboot[master]: mb/google/rex: LZ4 compress ramstage instead of LZMA
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Jamie Ryu, Kapil Porwal, Paul Menzel, Raj Astekar, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: LZ4 compress ramstage instead of LZMA ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > > > `dev` build is failing due to insufficient size. > > @Kapil, can u specify which build command is failing. I tried the release and debug build it's working fine. > > additionally, tried to enable the `FW_CONSOLE` using use flag, still don't see any issue. although I haven't seen the failure myself but I can sense the issue is due to not having ample space inside RW-A/RW-B to accommodate the 70KB+ size increase -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 10:10:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/spr-sp: Remove HWP related settings
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Paul Menzel, Tim Chu, Ziang Wang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75741?usp=email ) Change subject: soc/intel/spr-sp: Remove HWP related settings ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Personally I also hope that we wont remove the capability to let coreboot own this as well instead of FSP, but dont want to over engineering it. What do the rest think? -- To view, visit https://review.coreboot.org/c/coreboot/+/75741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee Gerrit-Change-Number: 75741 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 09:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Singer, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 10 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 09:57:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Add max memory speed into dimm info
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Johnny Lin, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75810?usp=email ) Change subject: soc/intel: Add max memory speed into dimm info ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Gerrit-Change-Number: 75810 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 09:54:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... soc/intel/xeon_sp: Fix HEST table length "current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01(a)inspur.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/xeon_sp/ras/hest.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c index 9eb54d9..2da720a 100644 --- a/src/soc/intel/xeon_sp/ras/hest.c +++ b/src/soc/intel/xeon_sp/ras/hest.c @@ -65,7 +65,7 @@ next = hest + 1; next += acpi_hest_add_ghes(next); hest->error_source_count += 1; - header->length += next - current; + header->length = next - current; return header->length; } -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 3 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Felix Singer (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jonathan Zhang, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, niehaitao(a)bytedance.com. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 6: (14 comments) File src/mainboard/bytedance/Kconfig: https://review.coreboot.org/c/coreboot/+/75722/comment/2fd33317_bcd1024b : PS6, Line 15: config MAINBOARD_FAMILY : default "Family" This is supposed to be configured in the mainboard Kconfig File src/mainboard/bytedance/bd_egs/Kconfig: https://review.coreboot.org/c/coreboot/+/75722/comment/37cdd1d4_c7c76f99 : PS6, Line 17: string no need to redefine types, remove https://review.coreboot.org/c/coreboot/+/75722/comment/e0bd56e9_134eb8ff : PS6, Line 21: string remove https://review.coreboot.org/c/coreboot/+/75722/comment/69191f4d_85734b61 : PS6, Line 25: string remove https://review.coreboot.org/c/coreboot/+/75722/comment/c68b5a25_11ecb759 : PS6, Line 29: int remove https://review.coreboot.org/c/coreboot/+/75722/comment/d5a2ace3_fd79a9d4 : PS6, Line 33: string remove File src/mainboard/bytedance/bd_egs/bootblock.c: https://review.coreboot.org/c/coreboot/+/75722/comment/8ef8d968_2fecee33 : PS6, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ Some of the files are licensed with GPL-2.0-or-later. Would you mind using it on the others as well? File src/mainboard/bytedance/bd_egs/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75722/comment/2ecf8e2b_d59f27bf : PS6, Line 4: # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs Seems superfluous, please remove File src/mainboard/bytedance/bd_egs/dsdt.asl: https://review.coreboot.org/c/coreboot/+/75722/comment/eda406a4_a4ae12c8 : PS6, Line 14: // platform ACPI tables Seems superfluous, please remove https://review.coreboot.org/c/coreboot/+/75722/comment/f9b436b4_0600d002 : PS6, Line 17: // global NVS and variables same https://review.coreboot.org/c/coreboot/+/75722/comment/2a1831d8_1b866dee : PS6, Line 22: // SPR-SP ACPI tables same https://review.coreboot.org/c/coreboot/+/75722/comment/c96cdc9e_829c6f4a : PS6, Line 25: // LPC related entries same File src/mainboard/bytedance/bd_egs/gpio.h: https://review.coreboot.org/c/coreboot/+/75722/comment/5761a6a7_1cc6c74c : PS6, Line 4: Missing header guards File src/mainboard/bytedance/bd_egs/ramstage.c: https://review.coreboot.org/c/coreboot/+/75722/comment/acffbcb8_7b41e65b : PS6, Line 8: void mainboard_silicon_init_params(FSPS_UPD *params) : { : } remove -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 6 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Wed, 14 Jun 2023 09:50:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Felix Singer (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75506/comment/b459b03f_28b32f46 : PS2, Line 339: return (unsigned long)ivrs; Why not just `return 0`? -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 09:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 09:02:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
by Dinesh Gehlot (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik. Hello Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75755?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot ...................................................................... soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot During a cold reboot, the CBMEM memory resets and loses the stored firmware versions. This causes the firmware versions to be fetched again from the CSE, which increases the boot time by about 200 ms. This patch stores a backup of the firmware version in CMOS and updates the CBMEM memory during a cold reboot. BUG=b:280722061 Test=Verified the changes on nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75755/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Gerrit-Change-Number: 75755 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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2017

2016

2015

2014

2013

coreboot-gerrit June 2023