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Change subject: device/device.h: Drop acpi_inject_dsdt
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
i agree that for things that can only be determined at runtime, an SSDT should be used
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Change subject: mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2ms
......................................................................
mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2ms
Reducing the polling time from 16ms to 2ms. Experimentally we
have determined that the link state normally takes approximately
3.5ms to update and therefore we were waiting longer than necessary.
TEST=build and confirm we are not waiting the extended period.
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Change-Id: I8fabb5ac46cae5c92d5b6f1dc0641a4d121c61dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76052
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/acpi/peg.asl
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/acpi/peg.asl b/src/mainboard/google/brya/acpi/peg.asl
index d0c76c8..ebaeaec 100644
--- a/src/mainboard/google/brya/acpi/peg.asl
+++ b/src/mainboard/google/brya/acpi/peg.asl
@@ -35,7 +35,7 @@
Break
}
- Sleep (16)
+ Sleep (2)
Local0--
}
NCB7 = 1
@@ -58,7 +58,7 @@
Break
}
- Sleep (16)
+ Sleep (2)
Local0--
}
@@ -71,7 +71,7 @@
Break
}
- Sleep (16)
+ Sleep (2)
Local0--
}
}
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(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brya/acpi: Set power down delay to 2ms after PEXVDD
......................................................................
mb/google/brya/acpi: Set power down delay to 2ms after PEXVDD
Reduce the delay between PEXVDD and NVVDD from 3ms to 2ms
during power down sequences. The hardware discharge is
aggressive enough that we can safely optimize this.
BUG=b:288267305
TEST=build and measured delay is acceptable
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Change-Id: I7c65301414044487e50bbbca618c4e602e571cfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76051
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/acpi/power.asl
M src/mainboard/google/brya/variants/hades/variant.c
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl
index a51bcaa..7eb31d8 100644
--- a/src/mainboard/google/brya/acpi/power.asl
+++ b/src/mainboard/google/brya/acpi/power.asl
@@ -140,7 +140,7 @@
#if CONFIG(BOARD_GOOGLE_AGAH)
Sleep (10)
#else
- Sleep (3)
+ Sleep (2)
#endif
/* Deassert EN_PPVAR_GPU_NVVDD */
@@ -290,7 +290,7 @@
#if CONFIG(BOARD_GOOGLE_AGAH)
Sleep (10)
#else
- Sleep (3)
+ Sleep (2)
#endif
/* Ramp down NVVDD */
diff --git a/src/mainboard/google/brya/variants/hades/variant.c b/src/mainboard/google/brya/variants/hades/variant.c
index 0864ec0..48e2652 100644
--- a/src/mainboard/google/brya/variants/hades/variant.c
+++ b/src/mainboard/google/brya/variants/hades/variant.c
@@ -61,7 +61,7 @@
/* In GCOFF entry order (i.e., power-off order) */
static struct power_rail_sequence gpu_off_seq[] = {
{ "FBVDD", FBVDD_PWR_EN, false, FBVDD_PG, 0,},
- { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 3,},
+ { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 2,},
{ "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,},
{ "GPU 3.3V", GPU_3V3_PWR_EN, false, GPU_3V3_PG, 4,},
{ "GPU 1.8V", GPU_1V8_PWR_EN, false, GPU_1V8_PG, 0,},
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Change subject: mb/google/brya/acpi: Don't wait for PG in GPU off sequences
......................................................................
mb/google/brya/acpi: Don't wait for PG in GPU off sequences
When powering rails down, there is no value in waiting for the PG
signal to de-assert. Instead, shut the rails off as quickly as possible
while maintaining a controlled ordering.
BUG=b:288266850
TEST=build and measured delays are gone
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Change-Id: If31691a7d62b72661fcbacb34e90f3a6adec8134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76050
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
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---
M src/mainboard/google/brya/acpi/power.asl
1 file changed, 3 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Nick Vaccaro: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl
index 5638e18..a51bcaa 100644
--- a/src/mainboard/google/brya/acpi/power.asl
+++ b/src/mainboard/google/brya/acpi/power.asl
@@ -137,7 +137,6 @@
/* Ramp down PEXVDD */
CTXS (GPIO_PEXVDD_PWR_EN)
- GPPL (GPIO_PEXVDD_PG, 0, 20)
#if CONFIG(BOARD_GOOGLE_AGAH)
Sleep (10)
#else
@@ -146,7 +145,6 @@
/* Deassert EN_PPVAR_GPU_NVVDD */
CTXS (GPIO_NVVDD_PWR_EN)
- GPPL (NVPG, 0, 20)
Sleep (2)
/* Assert GPU_PERST_L */
@@ -280,40 +278,34 @@
CTXS (GPIO_GPU_ALLRAILS_PG)
Sleep (1)
- /* Ramp down FBVDD and let rail discharge to <10% */
+ /* Ramp down FBVDD */
#if CONFIG(BOARD_GOOGLE_AGAH)
STXS (GPIO_FBVDD_PWR_EN)
#else
CTXS (GPIO_FBVDD_PWR_EN)
#endif
- GPPL (GPIO_FBVDD_PG, 0, 20)
/* Ramp down PEXVDD and let rail discharge to <10% */
CTXS (GPIO_PEXVDD_PWR_EN)
- GPPL (GPIO_PEXVDD_PG, 0, 20)
#if CONFIG(BOARD_GOOGLE_AGAH)
Sleep (10)
#else
Sleep (3)
#endif
- /* Ramp down NVVDD and let rail discharge to <10% */
+ /* Ramp down NVVDD */
CTXS (GPIO_NVVDD_PWR_EN)
- GPPL (NVPG, 0, 20)
Sleep (2)
- /* Ramp down NV33 and let rail discharge to <10% */
+ /* Ramp down NV33 */
CTXS (GPIO_NV33_PWR_EN)
- GPPL (GPIO_NV33_PG, 0, 20)
Sleep (4)
/* Ramp down 1.8V */
CTXS (GPEN)
- GPPL (GPIO_1V8_PG, 0, 20)
/* Ramp down 1.2V rail on boards with support */
CTXS (GPIO_NV12_PWR_EN)
- GPPL (GPIO_NV12_PG, 0, 5)
GCOT = Timer
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Change subject: Makefile.inc: don't add fmap_config.h dependency twice
......................................................................
Patch Set 2: Code-Review+1
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Change subject: Makefile.inc: fix multiple jobs build issue
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Should we put that in a follow-up?
Stupid question from my end, when a change is already merge (I didn't realize until now) :D
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Change subject: mb/google/rex: Enable audio BT offload with soundwire audio
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/rex/variants/rex0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/75924/comment/afe94f09_9ec7f4ae :
PS4, Line 94: printk(BIOS_INFO, "Configure GPIOs for BT offload mode with soundwire audio.\n");
: GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
> As both the changes are related to BT offload - cant this be done in this?
go ahead
https://review.coreboot.org/c/coreboot/+/75924/comment/8994d5e0_80a7b494 :
PS4, Line 99: Configure GPIOs for BT offload mode.
may be a seperate CL ?
```
Configure GPIOs for BT offload mode with I2S audio ?
```
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Change subject: mb/google/rex: Enable audio BT offload with soundwire audio
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/rex/variants/rex0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/75924/comment/fd8b3d95_9be5e7a6 :
PS4, Line 94: printk(BIOS_INFO, "Configure GPIOs for BT offload mode with soundwire audio.\n");
: GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
> this should be a separate CL
As both the changes are related to BT offload - cant this be done in this?
File src/mainboard/google/rex/variants/rex0/variant.c:
https://review.coreboot.org/c/coreboot/+/75924/comment/67e145b2_35e0ede5 :
PS4, Line 33: config->cnvi_bt_audio_offload |= fw_config_probe(FW_CONFIG(AUDIO,
: MAX98363_CS42L42_SNDW));
> WDYT? […]
Done
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Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: mb/google/rex: Enable audio BT offload with soundwire audio
......................................................................
mb/google/rex: Enable audio BT offload with soundwire audio
This patch enables BT offload feature on Rex over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3
Signed-off-by: Uday M Bhat <uday.m.bhat(a)intel.com>
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
M src/mainboard/google/rex/variants/rex0/variant.c
2 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/75924/5
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