coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/rex: Enable audio BT offload on rex soundwire device
by Uday Bhat (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Uday Bhat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75924?usp=email ) Change subject: mb/google/rex: Enable audio BT offload on rex soundwire device ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75924/comment/baeec5fa_3c08500e : PS4, Line 94: printk(BIOS_INFO, "Configure GPIOs for BT offload mode with soundwire audio.\n"); : GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads); > Created separate patch for https://review.coreboot. […] Merged back the changes back to this patch https://review.coreboot.org/c/coreboot/+/75924/comment/4f8d7900_cd0aaf4f : PS4, Line 99: Configure GPIOs for BT offload mode. > Updated to Configure GPIOs for BT I2S offload mode in https://review.coreboot. […] Merged back the changes back to this patch. Logging print is changed -- To view, visit https://review.coreboot.org/c/coreboot/+/75924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Gerrit-Change-Number: 75924 Gerrit-PatchSet: 7 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 14:10:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Enable GPIO for BT I2S offload for soundwire config
by Uday Bhat (Code Review) 23 Jun '23

23 Jun '23

Uday Bhat has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76003?usp=email ) Change subject: mb/google/rex: Enable GPIO for BT I2S offload for soundwire config ...................................................................... Abandoned Merged the changes back to https://review.coreboot.org/c/coreboot/+/75924 -- To view, visit https://review.coreboot.org/c/coreboot/+/76003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65eae8839d72b266f5239a694c7e57cec856eedf Gerrit-Change-Number: 76003 Gerrit-PatchSet: 3 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/google/rex: Enable audio BT offload on rex soundwire device
by Uday Bhat (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75924?usp=email to look at the new patch set (#7). Change subject: mb/google/rex: Enable audio BT offload on rex soundwire device ...................................................................... mb/google/rex: Enable audio BT offload on rex soundwire device This patch enables BT offload feature on rex soundwire device over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=build and verify BT offload on rex soundwire device Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Signed-off-by: Uday M Bhat <uday.m.bhat(a)intel.com> --- M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/variant.c 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/75924/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Gerrit-Change-Number: 75924 Gerrit-PatchSet: 7 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/amd/birman/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS
by Fred Reitberger (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76094?usp=email ) Change subject: mb/amd/birman/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS ...................................................................... mb/amd/birman/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS Always exit 4-byte addressing mode to prevent errors when the spi flash is not left in 4-byte addressing mode. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622 --- M src/mainboard/amd/birman/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/76094/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index d7fd1a5..95115ee 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -15,7 +15,8 @@ select PCIEXP_L1_SUB_STATE select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED - select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS config FMDFILE default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA -- To view, visit https://review.coreboot.org/c/coreboot/+/76094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622 Gerrit-Change-Number: 76094 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/spi_flash: Add option to always exit 4-byte address mode
by Fred Reitberger (Code Review) 23 Jun '23

23 Jun '23

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76093?usp=email ) Change subject: drivers/spi_flash: Add option to always exit 4-byte address mode ...................................................................... drivers/spi_flash: Add option to always exit 4-byte address mode Add Kconfig option to always send the Exit 4-Byte Address Mode (E9h) command before the first access to the SPI flash in all stages. This is useful for mainboards that do not access SPI flash in bootblock yet still need to exit 4-byte addressing mode in romstage or ramstage. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf --- M src/drivers/spi/Kconfig M src/drivers/spi/spi_flash.c 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/76093/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 8c251d7..e5ea447 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -173,6 +173,15 @@ On flashes that don't support 4-byte addressing mode or where it is already disabled, this command should be a no-op. +config SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS + bool + default n + depends on SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + help + This will send an Exit 4-Byte Address Mode (E9h) command before the first + access to the SPI flash in all stages. Otherwise, this command is only + sent in the initial stage (Bootblock or Verstage when before bootblock). + config SPI_FLASH_FORCE_4_BYTE_ADDR_MODE bool default n diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 5182684..cf74bf9 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -18,6 +18,9 @@ #define ADDR_MOD 0 #endif +#define SPI_FLASH_EXIT_4BYTE_STAGE \ + (ENV_INITIAL_STAGE || CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE_ALWAYS)) + static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ @@ -548,8 +551,10 @@ CONFIG_ROM_SIZE); } - if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && ENV_INITIAL_STAGE) + if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && SPI_FLASH_EXIT_4BYTE_STAGE) { + printk(BIOS_DEBUG, "SF: Exiting 4-byte addressing mode\n"); spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); + } return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/76093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf Gerrit-Change-Number: 76093 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Rename shared SRAM aliases
by Subrata Banik (Code Review) 23 Jun '23

23 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75999?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Rename shared SRAM aliases ...................................................................... soc/intel/meteorlake: Rename shared SRAM aliases Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/soc/intel/meteorlake/chipset.cb 4 files changed, 5 insertions(+), 5 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 9a71e95..bfe991b 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -57,7 +57,7 @@ device ref igpu on end device ref dtt on end device ref xhci on end - device ref shared_sram on end + device ref pmc_shared_sram on end device ref heci1 on end device ref uart0 on end device ref soc_espi on diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index bd5b0bb..5297ce2 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -71,7 +71,7 @@ device ref igpu on end device ref dtt on end device ref xhci on end - device ref shared_sram on end + device ref pmc_shared_sram on end device ref heci1 on end device ref uart0 on end device ref soc_espi on diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 05a61be..b7ce90d 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -583,7 +583,7 @@ end # I2C3 device ref i2c4 on end device ref i2c5 on end - device ref shared_sram on end + device ref pmc_shared_sram on end device ref uart0 on end device ref gspi1 on end device ref smbus on end diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 6a9c26a..b98e4f3 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -83,7 +83,7 @@ device pci 13.0 alias ioe_p2sb hidden end device pci 13.1 alias ieh2 off end device pci 13.2 alias pmc2 hidden end - device pci 13.3 alias shared_sram2 off end + device pci 13.3 alias ioe_shared_sram off end device pci 14.0 alias xhci off chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" @@ -128,7 +128,7 @@ end end device pci 14.1 alias usb_otg off end - device pci 14.2 alias shared_sram off end + device pci 14.2 alias pmc_shared_sram off end device pci 14.3 alias cnvi_wifi off end device pci 14.5 alias ieh off end device pci 15.0 alias i2c0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/75999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Gerrit-Change-Number: 75999 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mainboard/google/rex: Enable crashlog
by Subrata Banik (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Pratikkumar V Prajapati, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74770?usp=email ) Change subject: mainboard/google/rex: Enable crashlog ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74770?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Gerrit-Change-Number: 74770 Gerrit-PatchSet: 22 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 13:45:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Keep CNVi PCI device enabled for Ovis
by Subrata Banik (Code Review) 23 Jun '23

23 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76001?usp=email ) Change subject: mb/google/rex: Keep CNVi PCI device enabled for Ovis ...................................................................... mb/google/rex: Keep CNVi PCI device enabled for Ovis The CNVi PCI device is required for the system to boot properly. By ensuring that this device is enabled, we can prevent the below error message from appearing and ensure that the system boots successfully. BUG=b:274421383 TEST=Able to build and boot google/ovis without any error. w/o this patch: [ERROR] CNVi WiFi is enabled without CNVi being enabled [ERROR] CNVi BT is enabled without CNVi being enabled Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 1af0a0e..a6d5c04 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -185,6 +185,14 @@ end end end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/76001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354 Gerrit-Change-Number: 76001 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally
by Subrata Banik (Code Review) 23 Jun '23

23 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75998?usp=email ) Change subject: soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally ...................................................................... soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally This patch introduces a newer config to store the CSE RW FW version into the CBMEM. Prior to that CSE RW FW version was fetched unconditionally and ended up increasing the boot time by 7ms to 20ms depending on the SoC arch (including CSE arch). The way to retrieve the CSE firmware version is by sending the HECI command to read the CSE Boot Partition (BP) info. The cost of sending HECI command to read the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,ensure this feature is platform specific and only enabled for the platformthat would like to store the CSE version into the CBMEM. TEST=Build and boot google/rex to avoid getting CSE RW FW version to save 18ms of the boot time. w/o this patch: 10:start of ramstage 722,215 (43) 17:starting LZ4 decompress (ignore for x86) 741,415 (19,200) w/ this patch: 10:start of ramstage 722,257 (43) 17:starting LZ4 decompress (ignore for x86) 723,777 (1,520) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 876ec51..dc53268 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,23 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_STORE_CSE_FW_VERSION + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + This configuration option stores CSE RW FW version in CBMEM area. + This information can be used to identify if the CSE firmware update is successful + by comparing the currently running CSE RW firmware version against CSE version + belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while + building the AP FW image). + + The way to retrieve the CSE firmware version is by sending the HECI command to + read the CSE Boot Partition (BP) info. The cost of sending HECI command to read + the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence, + ensure this feature is platform specific and only enabled for the platform + that would like to store the CSE version into the CBMEM. + config SOC_INTEL_STORE_ISH_FW_VERSION bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ea956a7..14637ce 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1438,7 +1438,7 @@ */ static void cse_final(struct device *dev) { - if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION)) intel_cse_get_rw_version(); /* * SoC user can have two options for sending EOP: diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index dd3f173..d3fcec7 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1304,7 +1304,8 @@ cse_fw_sync(); /* Store the CSE RW Firmware Version into CBMEM */ - cse_store_rw_fw_version(); + if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION)) + cse_store_rw_fw_version(); /* * Store the ISH RW Firmware Version into CBMEM if ISH partition * is available -- To view, visit https://review.coreboot.org/c/coreboot/+/75998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32 Gerrit-Change-Number: 75998 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: acpi/acpigen.c: Ignore compiler warning about stack overflowing
by Nico Huber (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Lance Zhao, Paul Menzel, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76007?usp=email ) Change subject: acpi/acpigen.c: Ignore compiler warning about stack overflowing ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I've played with getting rid of the array, doesn't quite like the diffstat, though: CB:76092. -- To view, visit https://review.coreboot.org/c/coreboot/+/76007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d Gerrit-Change-Number: 76007 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 23 Jun 2023 13:06:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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