coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: intelblocks/pep: Send All Monitor Off/On command only in FWCM case
by Hannah Williams (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Balaji Manigandan, Felix Singer, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik, Tarun Tuli, Utkarsh H Patel, Utkarsh H Patel, Vikrant Jadeja. Hannah Williams has uploaded a new patch set (#8) to the change originally created by Usha P. ( https://review.coreboot.org/c/coreboot/+/75717?usp=email ) Change subject: intelblocks/pep: Send All Monitor Off/On command only in FWCM case ...................................................................... intelblocks/pep: Send All Monitor Off/On command only in FWCM case ALL_MONITOR_OFF command is sent using DPOF. IOM needs to be notified about ALL_MONITOR_OFF(TBT Displays OFF) only when Firmware Connection Manager(FWCM) is in use during S0ix Entry/Exit. When configured for SWCM this command should not be sent. BUG=SYSCROS-93267 TEST= Build and boot Rex Proto-1. Verify S0ix working. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/75717/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Gerrit-Change-Number: 75717 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: don't add fmap_config.h dependency twice
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76002?usp=email ) Change subject: Makefile.inc: don't add fmap_config.h dependency twice ...................................................................... Makefile.inc: don't add fmap_config.h dependency twice Commit d054bbd4f1ba ("Makefile.inc: fix multiple jobs build issue") added a dependency on $(obj)/fmap_config.h to all .c source files in all stages, so it's not needed any more to add it as a dependency to files that include fmap_config.h. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/drivers/smmstore/Makefile.inc M src/lib/Makefile.inc M src/security/vboot/Makefile.inc M src/soc/amd/common/block/apob/Makefile.inc M src/vendorcode/eltan/security/verified_boot/Makefile.inc 5 files changed, 1 insertion(+), 32 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/smmstore/Makefile.inc b/src/drivers/smmstore/Makefile.inc index 1c2e336..b37637b 100644 --- a/src/drivers/smmstore/Makefile.inc +++ b/src/drivers/smmstore/Makefile.inc @@ -1,13 +1,5 @@ all-$(CONFIG_SMMSTORE) += store.c -ifeq ($(CONFIG_SMMSTORE),y) -$(call src-to-obj,bootblock,$(dir)/store.c) : $(obj)/fmap_config.h -$(call src-to-obj,verstage,$(dir)/store.c) : $(obj)/fmap_config.h -$(call src-to-obj,romstage,$(dir)/store.c) : $(obj)/fmap_config.h -$(call src-to-obj,postcar,$(dir)/store.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/store.c) : $(obj)/fmap_config.h -$(call src-to-obj,smm,$(dir)/store.c) : $(obj)/fmap_config.h -endif ramstage-$(CONFIG_SMMSTORE_V2) += ramstage.c smm-$(CONFIG_SMMSTORE) += store.c smi.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 28e8dd3..53ff2d3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -241,13 +241,6 @@ $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/fmap.c) : $(obj)/fmap_config.h -$(call src-to-obj,romstage,$(dir)/fmap.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/fmap.c) : $(obj)/fmap_config.h -$(call src-to-obj,smm,$(dir)/fmap.c) : $(obj)/fmap_config.h -$(call src-to-obj,verstage,$(dir)/fmap.c) : $(obj)/fmap_config.h -$(call src-to-obj,postcar,$(dir)/fmap.c) : $(obj)/fmap_config.h - bootblock-y += bootmode.c romstage-y += bootmode.c ramstage-y += bootmode.c @@ -412,10 +405,7 @@ cbfs_master_header-type := "cbfs header" cbfs_master_header-position := 0 -ifeq ($(CONFIG_ARCH_X86),y) -$(call src-to-obj,bootblock,$(dir)/master_header_pointer.c): $(obj)/fmap_config.h -bootblock-y += master_header_pointer.c -endif +bootblock-$(CONFIG_ARCH_X86) += master_header_pointer.c NEED_CBFS_POINTER= diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ba83c3b..62a5660 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -73,11 +73,6 @@ ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c -$(call src-to-obj,bootblock,$(dir)/vbnv_flash.c) : $(obj)/fmap_config.h -$(call src-to-obj,verstage,$(dir)/vbnv_flash.c) : $(obj)/fmap_config.h -$(call src-to-obj,romstage,$(dir)/vbnv_flash.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/vbnv_flash.c) : $(obj)/fmap_config.h -$(call src-to-obj,postcar,$(dir)/vbnv_flash.c) : $(obj)/fmap_config.h bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc index 746e015..ae550bc 100644 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ b/src/soc/amd/common/block/apob/Makefile.inc @@ -3,7 +3,4 @@ romstage-y += apob_cache.c ramstage-y += apob_cache.c -$(call src-to-obj,romstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h - endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index aef8194..9158760 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -10,11 +10,6 @@ romstage-y += vboot_check.c ramstage-y += vboot_check.c -$(call src-to-obj,bootblock,$(dir)/vboot_check.c) : $(obj)/fmap_config.h -$(call src-to-obj,postcar,$(dir)/vboot_check.c) : $(obj)/fmap_config.h -$(call src-to-obj,romstage,$(dir)/vboot_check.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/vboot_check.c) : $(obj)/fmap_config.h - ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT),y) cbfs-files-y += oemmanifest.bin oemmanifest.bin-file := $(obj)/oemmanifest.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/76002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Gerrit-Change-Number: 76002 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: Rename CBFS master header -> CBFS main header
by Martin Roth (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Angel Pons, Jason Glenesk, Julius Werner, Martin L Roth, Stefan Reinauer. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75707?usp=email ) Change subject: Rename CBFS master header -> CBFS main header ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75707/comment/1ad86cf0_b42682f0 : PS5, Line 9: Calling it the main header is more descriptive of its pupose : and should therefore be preferred. > How about calling it "CBFS legacy header" to indicate that it is old and deprecated (although for pr […] I second the "CBFS legacy header" suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/75707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I624da280dd78d707b96897b84768be5f5baf0770 Gerrit-Change-Number: 75707 Gerrit-PatchSet: 7 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 16:27:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Makefile.inc: don't add fmap_config.h dependency twice
by Martin Roth (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Erik van den Bogaert, Felix Held, Frans Hendriks, Jason Glenesk, Julius Werner, Martin L Roth, Matt DeVillier, Raul Rangel, Yu-Ping Wu. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76002?usp=email ) Change subject: Makefile.inc: don't add fmap_config.h dependency twice ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Gerrit-Change-Number: 76002 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 23 Jun 2023 16:26:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: intelblocks/pep: Send All Monitor Off/On command only in FWCM case
by Hannah Williams (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Balaji Manigandan, Felix Singer, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik, Tarun Tuli, Utkarsh H Patel, Utkarsh H Patel, Vikrant Jadeja. Hannah Williams has uploaded a new patch set (#7) to the change originally created by Usha P. ( https://review.coreboot.org/c/coreboot/+/75717?usp=email ) Change subject: intelblocks/pep: Send All Monitor Off/On command only in FWCM case ...................................................................... intelblocks/pep: Send All Monitor Off/On command only in FWCM case ALL_MONITOR_OFF command is sent using DPOF. IOM needs to be notified about ALL_MONITOR_OFF(TBT Displays OFF) only when Firmware Connection Manager(FWCM) is in use during S0ix Entry/Exit. When configured for SWCM this command should not be sent. TEST= Build and boot Rex Proto-1. Verify S0ix working. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/75717/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Gerrit-Change-Number: 75717 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/brya: Add support for variant_memcfg_init()
by David Wu (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Bob Moragues, Eric Lai, Kane Chen, Nick Vaccaro, Tarun Tuli. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75990?usp=email ) Change subject: mb/google/brya: Add support for variant_memcfg_init() ...................................................................... Patch Set 1: (1 comment) This change is ready for review. Patchset: PS1: > That's right. Thanks. Sorry, I misunderstood. According to your suggestion (the same as CL:4623327), it will copy the duplicated data. The variant_memcfg_init() can help variant only update CsPiStartHighinEct to 1 if determine the DUT is using the hynix part. -- To view, visit https://review.coreboot.org/c/coreboot/+/75990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4926139e36602f87c8317ab4b476636e02f87771 Gerrit-Change-Number: 75990 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 16:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/xeon_sp: Redesign resource allocation
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Anjaneya "Reddy" Chagam, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Nico Huber, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67020?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/67020/comment/6122febd_1db3e133 : PS1, Line 53: res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > Are these indeed subtractive? i.e. can another device (not below this […] from what i heard, this is probably decoded positively on intel server cpus and not subtractively. on amd it's definitely positively decoded, so i dropped the IORESOURCE_SUBTRACTIVE flag there; see https://review.coreboot.org/c/coreboot/+/74717/19/src/soc/amd/common/block/… -- To view, visit https://review.coreboot.org/c/coreboot/+/67020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55c215fe078892e422a21ec1ca234faf8965542 Gerrit-Change-Number: 67020 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 16:06:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/skyrim/variants/baseboard:Update system_configuration
by Tim Van Patten (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Jason Glenesk, Jason Nien, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76091?usp=email ) Change subject: mb/google/skyrim/variants/baseboard:Update system_configuration ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76091/comment/2310538f_8fdd386b : PS2, Line 9: FT6 : Infrastructure Roadmap"#57316 Is there an AMD bug to update the documentation for future SOCs? https://review.coreboot.org/c/coreboot/+/76091/comment/d7038cf4_933d6483 : PS2, Line 12: Both SMU and FSP interpret configs > 3 as 3. Why does this require an extra call to the SMU to be performed, since it sounds like something they'd just handle on their own when given a value > 3? https://review.coreboot.org/c/coreboot/+/76091/comment/53c37334_6f56844b : PS2, Line 15: TEST=Confirm extra message is not sent in serial log. Is there any validation of the DPTC settings themselves that can be done, to verify the new value doesn't cause a power/performance regression? File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: PS2: This change also needs to be made in `src/mainboard/google/skyrim/variants/winterhold/overridetree.cb`: ``` # Refer the spec "FT6 Infrastructure Roadmap"#57316 # Set system_configuration to 4 for 15W register "system_configuration" = "4" ``` https://review.coreboot.org/c/coreboot/+/76091/comment/1d42e890_b6be6103 : PS2, Line 264: # DPTC: Refer the spec "FT6 Infrastructure Roadmap"#57316 : # Set system_configuration to 3 for 15W : register "system_configuration" = "3" I think it would be good to add a comment here that the document is actually wrong, and why using `3` is the better/correct choice. -- To view, visit https://review.coreboot.org/c/coreboot/+/76091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626 Gerrit-Change-Number: 76091 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 15:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/qemu-aarch64: Move probing dram to read_resources
by Lean Sheng Tan (Code Review) 23 Jun '23

23 Jun '23

Attention is currently required from: Arthur Heymans, David Milosevic, Maximilian Brune. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76004?usp=email ) Change subject: mb/qemu-aarch64: Move probing dram to read_resources ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaee41aec7806287ef1881372ec8ec47a4cd57d9 Gerrit-Change-Number: 76004 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 23 Jun 2023 15:23:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by Felix Held (Code Review) 23 Jun '23

23 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... soc/intel/jasperlake: Add per-SKU power limits Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni(a)intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni(a)intel.com> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/include/device/pci_ids.h M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/blipper/overridetree.cb M src/mainboard/google/dedede/variants/dibbi/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/haboki/overridetree.cb M src/mainboard/google/dedede/variants/kracko/overridetree.cb M src/mainboard/google/dedede/variants/lalala/overridetree.cb M src/mainboard/google/dedede/variants/lantis/overridetree.cb M src/mainboard/google/dedede/variants/madoo/overridetree.cb M src/mainboard/google/dedede/variants/magolor/overridetree.cb M src/mainboard/google/dedede/variants/metaknight/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/shotzo/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/systemagent.c 18 files changed, 202 insertions(+), 41 deletions(-) Approvals: Sumeet R Pawnikar: Looks good to me, approved Michał Żygowski: Looks good to me, approved Super Ni: Looks good to me, but someone else must approve build bot (Jenkins): Verified Super Ni: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 40df090..418f9e0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4135,6 +4135,7 @@ #define PCI_DID_INTEL_JSL_ID_3 0x4e12 #define PCI_DID_INTEL_JSL_ID_4 0x4e14 #define PCI_DID_INTEL_JSL_ID_5 0x4e24 +#define PCI_DID_INTEL_JSL_ID_6 0x4e28 #define PCI_DID_INTEL_ADL_S_ID_1 0x4660 #define PCI_DID_INTEL_ADL_S_ID_2 0x4664 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 30a971c..9f747d9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -166,11 +166,37 @@ # Enable DPTF register "dptf_enable" = "1" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 20, }" + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N4505_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N5105_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N6005_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + register "tcc_offset" = "10" # TCC of 90C # VR config settings diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index 518b962..a507dd1 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -59,11 +59,6 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C # Enable Acoustic noise mitigation and set slew rate to 1/8 diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index e3df1f2..6cda586 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -25,6 +25,19 @@ }, }" + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + # Enable Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 2eb9d81..e90d97e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -64,11 +64,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "20" # TCC of 85C # Enable Acoustic noise mitigation and set slew rate to 1/4 diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb index cffcc9a..704e458 100644 --- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb @@ -35,11 +35,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "20" # TCC of 85C register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0 diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 1ce3a8f..5e39c88 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -65,11 +65,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "20" # TCC of 85C device domain 0 on diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb index fe3c407..7b849b2 100644 --- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb @@ -56,7 +56,18 @@ }, }" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 12, }" diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index b67bd97..c568408 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -72,7 +72,18 @@ }, }" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 15, }" diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 2260652..437c60a 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -54,11 +54,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C # Enable Acoustic noise mitigation and set slew rate to 1/8 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index bb5bf244..cde69ed 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -95,7 +95,18 @@ }, }" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 12, }" diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 75618f4..e01dee9 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -64,7 +64,18 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 12, }" diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 43a68db..5e4de2a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -87,11 +87,6 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Camera - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C register "xhci_lfps_sampling_offtime_ms" = "0" diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb index b454e3d..0935457 100644 --- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb @@ -40,7 +40,18 @@ register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 25, }" diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 3b1f007..1aa2e71 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -84,7 +84,18 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "power_limits_config" = "{ + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 20, }" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fdd1a78..957ab1d 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -124,11 +124,36 @@ register "dptf_enable" = "1" # Add PL1 and PL2 values - register "power_limits_config" = "{ + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 20, }" + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N4505_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N5105_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N6005_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + }" + # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index e6b8f680..b986f18 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -3,6 +3,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <device/pci_ids.h> #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> #include <drivers/intel/gma/gma.h> @@ -23,13 +24,44 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 +/* Types of different SKUs */ +enum soc_intel_jasperlake_power_limits { + JSL_N4500_6W_CORE, + JSL_N6000_6W_CORE, + JSL_N5100_6W_CORE, + JSL_N4505_10W_CORE, + JSL_N5105_10W_CORE, + JSL_N6005_10W_CORE, + JSL_POWER_LIMITS_COUNT +}; + +/* TDP values for different SKUs */ +enum soc_intel_jasperlake_cpu_tdps { + TDP_6W = 6, + TDP_10W = 10 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int pci_did; + enum soc_intel_jasperlake_power_limits limits; + enum soc_intel_jasperlake_cpu_tdps cpu_tdp; +} cpuid_to_jsl[] = { + { PCI_DID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W }, + { PCI_DID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W }, + { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W }, +}; + struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index fd04be5..f0e9d44 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <chip.h> +#include <console/console.h> #include <device/device.h> #include <delay.h> #include <device/pci.h> @@ -48,6 +50,9 @@ { struct soc_power_limits_config *soc_config; config_t *config; + uint16_t sa_pci_id; + uint8_t tdp; + size_t i = 0; /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -57,6 +62,29 @@ mdelay(1); config = config_of_soc(); - soc_config = &config->power_limits_config; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + + /* Get System Agent PCI ID */ + sa_pci_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xFFFF; + + if (sa_pci_id != 0xFFFF) { + tdp = get_cpu_tdp(); + + /* Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) { + if (sa_pci_id == cpuid_to_jsl[i].pci_did && + tdp == cpuid_to_jsl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_jsl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + break; + } + } + } + + if (i == ARRAY_SIZE(cpuid_to_jsl) || sa_pci_id == 0xFFFF) { + printk(BIOS_ERR, "unknown SA ID: 0x%4x, can't find its TDP." + " Skipped power limits configuration.\n", + sa_pci_id); + return; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 15 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Super Ni <super.ni(a)intel.com> Gerrit-Reviewer: Super Ni <super.ni(a)intel.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2023