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Change subject: mb/google/myst: Declare CrOS GPIOs
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/myst/Kconfig:
https://review.coreboot.org/c/coreboot/+/74111/comment/6882d63a_898af3dc
PS4, Line 38: default 0x03
Should this be 0x2?
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74111/comment/ebe6b051_af0a4329
PS4, Line 136: device i2c 50 on end
Should this be GPIO_84?
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Change subject: mb/google/myst: Add stubs to configure GPIOs
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Patch Set 3: Code-Review+1
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Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74150/comment/6cadefd3_830c99a8
PS2, Line 11: all
> single-quote for clarity
Done
https://review.coreboot.org/c/coreboot/+/74150/comment/d05bb3f0_8b8acf7c
PS2, Line 14: omstage
> oxford comma
i think that the oxford comma looks quite bad, but i'm not the native english speaker here, so i'll just add it
https://review.coreboot.org/c/coreboot/+/74150/comment/606b6bb9_a47a6e95
PS2, Line 14: verstage_x88
> _x86
Done
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Hello build bot (Jenkins), Martin L Roth, Matt DeVillier,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Makefile.inc: introduce all_x86 target
For compilation units that should be built for all stages that run on
the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP
which is an ARM core, the 'all' target can't be used, since that would
result in the compilation unit also being added to the verstage target
in the verstage on PSP case. In order to not need to add a compilation
unit to bootblock, verstage_x86, romstage, and ramstage in separate
lines in the makefile, introduce the all_x86 target that adds a file to
bootblock, verstage_x86, romstage, postcar, ramstage. The compilation
units also need to be added to the postcar stage which is only present
on the pre-Zen SoCs to be able to also use the all_x86 target in common
AMD code that is also used in those pre-Zen SoCs.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e
---
M Makefile.inc
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74150/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/qualcomm/sc7280: Check domain enabled before assigning pci ops
......................................................................
soc/qualcomm/sc7280: Check domain enabled before assigning pci ops
Make sure that DOMAIN is enabled before checking if pcie device should
be enabled. This removes the call to the EC for the SKU id from the
mainboard_needs_pcie_init() call.
BUG=b:262586570
BRANCH=None
TEST=Make sure that pcie is not being initialized for eMMC skus
through cbmem output when DOMAIN and pci devices are disabled
in the device tree.
Signed-off-by: Shelley Chen <shchen(a)google.com>
Change-Id: I772c426ac2dd3f296590b1bc40f8649eb3db3d5f
---
M src/soc/qualcomm/sc7280/soc.c
1 file changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/73716/2
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Change subject: payloads/edk2: Set max variable size to 0x8000 for SMMSTORE
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Why not squash it into the SMMSTORE patch? I'm starting to use: […]
I don't disagree there - but this is the one major patch we can't merge upstream. Bit hacky, but we could have the smmstore patches in Gerrit, and make make cherry pick them base on smmstore kconfig?
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