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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: mb/google/myst: Add eSPI configuration
......................................................................
mb/google/myst: Add eSPI configuration
Add eSPI configuration for myst. Ensure the additional windows are used
and remove unnecessary addresses from the range used on skyrim.
BUG=b:275953893
TEST=builds
Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
2 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74110/7
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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74111/comment/61baaa8f_ce78c4bc
PS8, Line 178: PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
> go/myst-gpios doesn't list these GPIOs (113, 114). […]
I was looking at the schematic:
https://ee-schematics.teams.x20web.corp.google.com/myst/myst/proto0/referen…
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 6:
(4 comments)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74110/comment/1a802722_3fb3b7df
PS6, Line 7: .generic_io_range[0] = {
: .base = 0x62,
: .size = 1,
: },
: .generic_io_range[1] = {
: .base = 0x66,
: .size = 1,
: },
> Why doesn't this comment apply to myst also? […]
Phoenix has additional windows. It actually looks like MDN does as well, so I'm not sure why we didn't fix this on Skyrim b/221095488
https://review.coreboot.org/c/coreboot/+/74110/comment/307d81e0_22b753d8
PS6, Line 29: .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
> For initial stability, should we start at 16MHz for bring up and then move up to 33?
Done
https://review.coreboot.org/c/coreboot/+/74110/comment/0bec83fa_5e65d5d9
PS6, Line 31: ESPI_ALERT_PIN_IN_BAND
> go/myst-gpios lists this as `ESPI_EC_ALERT_SOC_ODL`, implying this should likely be `ESPI_ALERT_PIN_ […]
Done
https://review.coreboot.org/c/coreboot/+/74110/comment/5b826409_f7630194
PS6, Line 37: ESPI_VW_IRQ_LEVEL_HIGH(12)
> IRQ12 was removed from skyrim (https://review.coreboot.org/c/coreboot/+/63704). […]
It's not, old copy paste. I need to cross check this CL against the one you referenced and where Skyrim is today.
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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74111/comment/f8d5262c_52c8f98d
PS8, Line 136: device i2c 50 on end
Do we need the `alias ti50`?
```
device i2c 50 alias ti50 on end
```
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74111/comment/9ac72606_c99d951a
PS8, Line 178: PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
go/myst-gpios doesn't list these GPIOs (113, 114). Where did they come from?
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Change subject: mb/google/myst: Add new mainboard
......................................................................
Patch Set 3:
(3 comments)
File src/mainboard/google/myst/Kconfig:
https://review.coreboot.org/c/coreboot/+/74093/comment/16ab8ea9_4a17e88b
PS3, Line 8: config AMD_FWM_POSITION_INDEX
: int
: default 3
Phoenix has a fixed EFS location (0x20000) so this config value has no effect
File src/mainboard/google/myst/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74093/comment/028b6d4d_ee665e14
PS2, Line 2: SI_BIOS {
> It seems a mix and match of Birman and Skyrim. […]
RECOVERY_MRC_CACHE should be 256K, same as the size of RW_MRC_CACHE
The EFS must exist at the 128K offset, so the RW_MRC_CACHE will not fit at the beginning of flash
File src/mainboard/google/myst/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74093/comment/9b45bcf9_4bebdbd7
PS3, Line 36: }
> Fred/Martin, […]
RO should cover the lowest flash offsets. See the birman `chromeos_phoenix.fmd` layout for an example.
As far as 32M layout, we have been testing putting the RO PSP binaries in the upper 16M and the rest of the image in the lower 16M half, but I don't think that will work long-term unless the flash chip supports two different write-protect ranges?
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Change subject: mb/google/myst: Add new mainboard
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/myst/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74093/comment/1633321a_e4198631
PS3, Line 36: }
> Fred/Martin, […]
sent you some code to have a look at. haven't had the time to really look into this whole topic yet
File src/mainboard/google/myst/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/74093/comment/b9a0ccb9_8e970279
PS2, Line 16: Name(LIDS, 0)
> Done
i'd say that it would be good if that was moved to the EC's acpi code to which this belongs, but that depends on some rework on the intel soc side which i'm not planning to do
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 6:
(4 comments)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74110/comment/74f93a2a_6c42e199
PS6, Line 7: .generic_io_range[0] = {
: .base = 0x62,
: .size = 1,
: },
: .generic_io_range[1] = {
: .base = 0x66,
: .size = 1,
: },
Why doesn't this comment apply to myst also?
```
/*
* Only 0x62 and 0x66 are required. But, this is not supported by
* standard IO decodes and there are only 4 generic I/O windows
* available. Hence, open a window from 0x62-0x67.
*/
```
https://review.coreboot.org/c/coreboot/+/74110/comment/fb5cdd78_3483e209
PS6, Line 29: .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
For initial stability, should we start at 16MHz for bring up and then move up to 33?
https://review.coreboot.org/c/coreboot/+/74110/comment/51d00fbf_60b40e5d
PS6, Line 31: ESPI_ALERT_PIN_IN_BAND
go/myst-gpios lists this as `ESPI_EC_ALERT_SOC_ODL`, implying this should likely be `ESPI_ALERT_PIN_OPEN_DRAIN`.
https://review.coreboot.org/c/coreboot/+/74110/comment/83bc3d2a_a23fb847
PS6, Line 37: ESPI_VW_IRQ_LEVEL_HIGH(12)
IRQ12 was removed from skyrim (https://review.coreboot.org/c/coreboot/+/63704). Why is it necessary again for myst?
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Change subject: mb/google/myst: Add initial fch irq routing
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74109/comment/9e960c96_74a0bf6e
PS5, Line 24: static const struct fch_irq_routing fch_irq_map[] = {
> These match skyrim. […]
They also match guybrush. I'm not sure about specific documentation. I can try to find something.
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Change subject: mb/google/myst: Add initial I2C configuration
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/myst/variants/myst/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74108/comment/94d582eb_27c76b92
PS5, Line 33: # I2C Config
> For skyrim, these live in `baseboard/devicetree.cb`. Is moving them here into `overridetree. […]
On Skyrim they started here I think and got moved later. I'm fine putting them in the baseboard devicetree.
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Change subject: mb/google/myst: Add initial fch irq routing
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74109/comment/4d70499c_c19be125
PS5, Line 24: static const struct fch_irq_routing fch_irq_map[] = {
These match skyrim. What can we look at to validate they are correct for myst too?
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