coreboot-gerrit April 2023

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[M] Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by Lean Sheng Tan (Code Review) 03 Apr '23

03 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62562 ) ( 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... option: Allow to use the EFI variable driver as option backend Use the introduced EFI variable store driver on top of the SMMSTORE region in SPI flash to read/write options. Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62562 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig A src/drivers/efi/option.c 2 files changed, 70 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 16f7881..e35df43 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -142,6 +142,8 @@ prompt "Option backend to use" default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD + default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \ + PAYLOAD_EDK2 && SMMSTORE_V2 config OPTION_BACKEND_NONE bool "None" @@ -153,6 +155,15 @@ Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values. +config USE_UEFI_VARIABLE_STORE + bool "Use UEFI variable-store in SPI flash as option backend" + depends on DRIVERS_EFI_VARIABLE_STORE + depends on SMMSTORE_V2 + help + Enable this option if coreboot shall read/write options from the + SMMSTORE region within the SPI flash. The region must be formatted + by the payload first before it can be used. + config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND bool "Use mainboard-specific option backend" depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c new file mode 100644 index 0000000..3960cfc --- /dev/null +++ b/src/drivers/efi/option.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <string.h> +#include <option.h> +#include <smmstore.h> + +#include <Uefi/UefiBaseType.h> + +#include "efivars.h" + +static const EFI_GUID EficorebootNvDataGuid = { + 0xceae4c1d, 0x335b, 0x4685, { 0xa4, 0xa0, 0xfc, 0x4a, 0x94, 0xee, 0xa0, 0x85 } }; + +unsigned int get_uint_option(const char *name, const unsigned int fallback) +{ + struct region_device rdev; + enum cb_err ret; + uint32_t var; + uint32_t size; + + if (smmstore_lookup_region(&rdev)) + return fallback; + + var = 0; + size = sizeof(var); + ret = efi_fv_get_option(&rdev, &EficorebootNvDataGuid, name, &var, &size); + if (ret != CB_SUCCESS) + return fallback; + + return var; +} + +enum cb_err set_uint_option(const char *name, unsigned int value) +{ + struct region_device rdev; + uint32_t var = value; + + if (smmstore_lookup_region(&rdev)) + return CB_CMOS_OTABLE_DISABLED; + + return efi_fv_set_option(&rdev, &EficorebootNvDataGuid, name, &var, sizeof(var)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 24 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elias Souza <eliascontato(a)protonmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi/acpigen: Add print-like function for debug string
by Cliff Huang (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Lance Zhao, Bora Guvendik, Hannah Williams, Jakub Czapiga, Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73113 ) Change subject: acpi/acpigen: Add print-like function for debug string ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73113/comment/ec552162_81626326 PS7, Line 7: acpi: Add print-like function for debug string > It's just the naming in the commit summary like this? acpi/acpigen and print/printf: Add print-like function for debug string -- To view, visit https://review.coreboot.org/c/coreboot/+/73113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Gerrit-Change-Number: 73113 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 21:14:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add root port mutex support
by Cliff Huang (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Hannah Williams, Anil Kumar K, Tarun Tuli, Angel Pons, Maximilian Brune. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73380 ) Change subject: soc/intel/common/block/pcie/rtd3: Add root port mutex support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73380/comment/59807dab_edb59cc5 PS2, Line 23: BRANCH=firmware-brya-14505.B > Is there a corresponding bug that goes with this? There is no direct bug, but the need of this mutex was observed while I was working on 241850118, where one case is doing WWAN reset and S0ix. -- To view, visit https://review.coreboot.org/c/coreboot/+/73380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc077528692b2d7076132384fb7bd441be502511 Gerrit-Change-Number: 73380 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 21:12:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update pcie snoop/no-snoop latency
by Bora Guvendik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Jérémy Compostella, Ravishankar Sarawadi, Kapil Porwal. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68308 ) Change subject: soc/intel/meteorlake: Update pcie snoop/no-snoop latency ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68308/comment/1869f11c_50703650 PS4, Line 9: Overwrite pcie max non-snoop and snoop latency tolerance values : for MTL. > also provide the override value. […] Done https://review.coreboot.org/c/coreboot/+/68308/comment/b80facb7_f41b5a9c PS4, Line 13: Boot to OS, check values. > which board ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Gerrit-Change-Number: 68308 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 21:08:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update pcie snoop/no-snoop latency
by Bora Guvendik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Jérémy Compostella, Ravishankar Sarawadi, Kapil Porwal. Bora Guvendik has uploaded a new patch set (#6) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/68308 ) Change subject: soc/intel/meteorlake: Update pcie snoop/no-snoop latency ...................................................................... soc/intel/meteorlake: Update pcie snoop/no-snoop latency Overwrite pcie max non-snoop and snoop latency tolerance values to 5242.88us for Meteor Lake. This fixes an issue where pcie was not power gating and blocked S0ix entry. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 --- M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/pcie.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/68308/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Gerrit-Change-Number: 68308 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmn/pcie: Add ability for SoC to overwrite snoop/no-snoop l...
by Bora Guvendik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Hannah Williams, Subrata Banik, Jérémy Compostella. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74141 ) Change subject: soc/intel/cmn/pcie: Add ability for SoC to overwrite snoop/no-snoop latency ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74141/comment/f6807816_f65a2d23 PS3, Line 7: common/pcie > soc/intel/cmn/pcie Done https://review.coreboot.org/c/coreboot/+/74141/comment/63854143_2b0c9f27 PS3, Line 13: Boot to OS and check if able to overwrite values. > which platform and how to check the overridden value ? Done Patchset: PS3: > please mention the default value here? […] PCIe was not power gated and blocked S0ix entry -- To view, visit https://review.coreboot.org/c/coreboot/+/74141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Gerrit-Change-Number: 74141 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 21:05:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable eSPI SCI events
by Raul Rangel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74101 ) Change subject: mb/google/myst: Enable eSPI SCI events ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/myst/ec.c: https://review.coreboot.org/c/coreboot/+/74101/comment/af3092f5_0e124306 PS6, Line 14: GEVENT_3 > > It does come from that sheet. […] We use a #define on guybrush to make it easier to understand: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… Normally you can pick any GEVENT as long as it's not used. GEVENTs 0-23(?) can be mapped to GPIOs if desired, 24-31 are internal only GEVENTs. So we generally use 24+. For xhci we use 31: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… -- To view, visit https://review.coreboot.org/c/coreboot/+/74101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Gerrit-Change-Number: 74101 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 21:02:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable eSPI SCI events
by Tim Van Patten (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74101 ) Change subject: mb/google/myst: Enable eSPI SCI events ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/myst/ec.c: https://review.coreboot.org/c/coreboot/+/74101/comment/bc5e43ad_ab978e49 PS6, Line 14: GEVENT_3 > It does come from that sheet. I'm probably missing it; can you point out where? > This was errantly left in from Skyrim. There isn't an event associated with the interrupt line on Myst. I'm not sure if that's problematic. Raul would probably know best, but I think we need this for the linux kernel to assign wake events to SCIs that come in (and make sure the correct wake counts are incremented, etc.). I'm not sure what's involved with getting one assigned though. -- To view, visit https://review.coreboot.org/c/coreboot/+/74101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Gerrit-Change-Number: 74101 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 20:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Build for chromeOS
by Tim Van Patten (Code Review) 03 Apr '23

03 Apr '23

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[S] Change in coreboot[master]: cpu/x86/64bit/Makefile: use all_x86 make target
by Matt DeVillier (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74197 ) Change subject: cpu/x86/64bit/Makefile: use all_x86 make target ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8950375d31557d9a38169869c1d250417261c31c Gerrit-Change-Number: 74197 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 03 Apr 2023 20:23:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023