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Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/skyrim: override Markarth PCIe config
......................................................................
Patch Set 3: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74147 )
Change subject: mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFI
......................................................................
mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFI
This patch avoids creating runtime ACPI for unused WIFI solutions.
For example: if the Rex SKU is with WIFI_CNVI then you don't need
to populate ACPI code for WIFI_PCIE.
FW_CONIG can be used for making those decisions.
TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is
set to WIFI_CNVI.
Also, helped to save the boot time on google/rex (FSP-S API) by 9ms.
Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147
Reviewed-by: YH Lin <yueherngl(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 35 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
YH Lin: Looks good to me, but someone else must approve
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 44d20cb..282c3da 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -248,7 +248,9 @@
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
- device generic 0 on end
+ device generic 0 on
+ probe WIFI WIFI_CNVI
+ end
end
end
device ref ipu on
@@ -500,6 +502,7 @@
end
end #I2C5
device ref pcie_rp5 on
+ probe WIFI WIFI_PCIE
# Enable WLAN Card PCIE 5 using clk 5
register "pcie_rp[PCH_RP(5)]" = "{
.clk_src = 5,
@@ -509,13 +512,17 @@
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_09"
register "add_acpi_dma_property" = "true"
- device pci 00.0 on end
+ device pci 00.0 on
+ probe WIFI WIFI_PCIE
+ end
end
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)"
register "srcclk_pin" = "5"
- device generic 0 on end
+ device generic 0 on
+ probe WIFI WIFI_PCIE
+ end
end
end #PCIE5 WLAN card
device ref pcie_rp6 on
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Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74113 )
Change subject: mb/google/myst: Configure WLAN
......................................................................
Patch Set 9:
(4 comments)
File src/mainboard/google/myst/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74113/comment/d6b57cf0_e33245d8
PS9, Line 5: romstage-y += gpio.c
nit: Move above `ramstage` to match previous boards.
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74113/comment/89b1c136_e07dd161
PS9, Line 193: static const struct soc_amd_gpio early_gpio_table[] = {
Where did these GPIO values come from?
https://review.coreboot.org/c/coreboot/+/74113/comment/1ed592b6_b5599752
PS9, Line 202: pcie_gpio_table
Skyrim defines this as `romstage_gpio_table`, which is used in `baseboard_romstage_gpio_table()`.
Why is this changed for Myst?
https://review.coreboot.org/c/coreboot/+/74113/comment/00e3807e_67ca639d
PS9, Line 228: __weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
This isn't defined for any other board. It's also not called anywhere.
This should likely be `baseboard_romstage_gpio_table()`.
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Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73380 )
Change subject: soc/intel/common/block/pcie/rtd3: Add root port mutex support
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73380/comment/8f86b2c9_755a7ce9
PS2, Line 23: BRANCH=firmware-brya-14505.B
Is there a corresponding bug that goes with this?
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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74111/comment/82a55f9a_f46a6206
PS8, Line 136: device i2c 50 on end
> Do we need the `alias ti50`? […]
Looks like that was added here https://review.coreboot.org/c/coreboot/+/69874 and may be needed for passing the IRQ to the PSP in the same way
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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74111/comment/0fef4ea1_315ded3c
PS8, Line 178: PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
> I was looking at the schematic: […]
go/myst-gpios does list GPIO 113 and 114, they're just muxed. Look at cumulative GPIO 60 and 61
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Change subject: acpi/acpigen: Add print-like function for debug string
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73113/comment/c01d05b2_56e93330
PS7, Line 7: acpi: Add print-like function for debug string
> not sure how to have both. I will change to acpi/acpigen since no changes in printf.
It's just the naming in the commit summary
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74112/comment/ee45606d_34db35ee
PS8, Line 43: device domain 0 on
Do we need `device ref iommu on end` so we can access these devices through the IOMMU?
https://review.coreboot.org/c/coreboot/+/74112/comment/7e046667_d04783b9
PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe
I'm not an expert here. Why are these `bridge_2_1`, `bridge_2_2`, etc., rather than just `bridge_1`, `bridge_2`, etc.?
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Hello build bot (Jenkins), Raul Rangel, Eric Lai, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74108
to look at the new patch set (#7).
Change subject: mb/google/myst: Add initial I2C configuration
......................................................................
mb/google/myst: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.
BUG=b:275939564
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/myst/overridetree.cb
3 files changed, 58 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74108/7
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