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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74370 )
Change subject: soc/intel/meteorlake: Replace assert with error message
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/74370/comment/032d64d7_2ee41a62
PS2, Line 568: if (!s_cfg->CnviMode && s_cfg->CnviWifiCore)
IIRC why we do this before is this will cause FSP/kernel panic. So we put assert at first time. But not sure about MTL FSP.
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Change subject: soc/intel/: Implement an API to get ISH version
......................................................................
Patch Set 10:
(4 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/9e2a8026_c3e8676d
PS9, Line 1277: /*
: * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a
: * default. This is intended for pre-mem usage only where BARs haven't been
: * assigned yet and devices are not enabled.
> May I know how this comment is connected with get_ish_version()?
Ack
https://review.coreboot.org/c/coreboot/+/74209/comment/8dc7f72c_9d6e458a
PS9, Line 1282: bool
> please prefer enum cb_err.
Ack
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74209/comment/2982c1ff_a73f8d06
PS9, Line 453: bool
> please prefer enum cb_err.
Ack
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74209/comment/2d218856_7dfdd3af
PS5, Line 547: if the latest ISH version is not updated in the CBMEM table
> Ah, you meant “not up to date”. […]
Ack
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Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74208 )
Change subject: soc/intel/: Store ISH firmware version into cbmem table
......................................................................
Patch Set 15:
(5 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74208/comment/e5fe2910_86d88490
PS14, Line 1278: FSP-M
> memory?
Ack
https://review.coreboot.org/c/coreboot/+/74208/comment/26bab3e2_cfdd16a2
PS14, Line 1279: CSE DRAM
> DRAM. […]
Ack
https://review.coreboot.org/c/coreboot/+/74208/comment/96b52d2b_bf4d6965
PS14, Line 1282: store_ish_version
> Can we move this definition to new file?
I believe the cse.c file is a good place to put the new API for the ISH because other relevant APIs are already there.
https://review.coreboot.org/c/coreboot/+/74208/comment/e0beef46_651cc5c3
PS14, Line 1305: version->ish_partition_info.prev_cse_fw_version.major
: = version->cur_cse_fw_version.major;
: version->ish_partition_info.prev_cse_fw_version.minor
: = version->cur_cse_fw_version.minor;
: version->ish_partition_info.prev_cse_fw_version.hotfix
: = version->cur_cse_fw_version.hotfix;
: version->ish_partition_info.prev_cse_fw_version.build
: = version->cur_cse_fw_version.build;
:
> can you define generic function for copying the version from src to destination? […]
Ack
https://review.coreboot.org/c/coreboot/+/74208/comment/d3c6a203_432b6da1
PS14, Line 1315: version->ish_partition_info.cur_ish_fw_version.major
: = resp.manifest_data.version.major;
: version->ish_partition_info.cur_ish_fw_version.minor
: = resp.manifest_data.version.minor;
: version->ish_partition_info.cur_ish_fw_version.hotfix
: = resp.manifest_data.version.hotfix;
: version->ish_partition_info.cur_ish_fw_version.build
: = resp.manifest_data.version.build;
> You may use generic version copy function (cse_copy_fw_version) for this as described above?
Ack
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Kyösti Mälkki has uploaded a new patch set (#26) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/69225 )
Change subject: acpi/acpi.c: Follow spec more closely for MADT
......................................................................
acpi/acpi.c: Follow spec more closely for MADT
Secondary threads need to be added after the primary threads.
Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/acpi/acpi.c
1 file changed, 41 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69225/26
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Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
Patch Set 29:
(7 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74005/comment/ab16bc66_720e49bb
PS28, Line 1218: bool
> Pleas use enum cb_err.
Ack
https://review.coreboot.org/c/coreboot/+/74005/comment/f0c023ef_956bd5a5
PS28, Line 1242: fw partition request
> Get Image Firmware Version command?
Ack
https://review.coreboot.org/c/coreboot/+/74005/comment/f3496822_70c55685
PS28, Line 1250: partition
> partition information for?
Ack
https://review.coreboot.org/c/coreboot/+/74005/comment/0abfc06c_58309f33
PS28, Line 1260: BIOS_INFO
> Should it be level warning or error?
Ack
https://review.coreboot.org/c/coreboot/+/74005/comment/18ecba90_e68657ca
PS28, Line 1259: if (vboot_recovery_mode_enabled()) {
: printk(BIOS_INFO, "CSE: Info request denied, request during recovery mode\n");
: return false;
: }
> I see you added the condition in the higher layer, so please remove it from here. […]
The API is standalone and exposed for generic use. Therefore, it is possible that the user may or may not have performed a recovery mode check before calling this API.
https://review.coreboot.org/c/coreboot/+/74005/comment/c22e4943_667dfc48
PS28, Line 1264: SOC_INTEL_CSE_LITE_SKU
> Please note cse_get_fpt_partition_info() is also applicable for non-CSE lite SKU and this file refer […]
Ack
https://review.coreboot.org/c/coreboot/+/74005/comment/66e4a639_934e3697
PS28, Line 1269: if (id == FPT_PARTITION_NAME_ISHC && !CONFIG(DRIVERS_INTEL_ISH)) {
: printk(BIOS_INFO, "CSE: Info request denied, no ISH partition\n");
: return false;
: }
:
> Can this moved to higher layer since this file contains CSE API Lib?
We could move the check to another location, but I believe it is best to perform all checks before calling the send_get_fpt_partition_info_cmd() function. Scattered checks throughout the call flow will make the code less readable.
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Change subject: soc/intel/: Implement an API to get ISH version
......................................................................
Patch Set 10:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174046):
https://review.coreboot.org/c/coreboot/+/74209/comment/266f233a_447cc373
PS10, Line 1299: cse_copy_fw_version(resp_version,&(version->ish_partition_info.cur_ish_fw_version));
space required after that ',' (ctx:VxO)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174046):
https://review.coreboot.org/c/coreboot/+/74209/comment/1d048644_3021abb4
PS10, Line 1299: cse_copy_fw_version(resp_version,&(version->ish_partition_info.cur_ish_fw_version));
space required before that '&' (ctx:OxV)
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Hello build bot (Jenkins), Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74209
to look at the new patch set (#10).
Change subject: soc/intel/: Implement an API to get ISH version
......................................................................
soc/intel/: Implement an API to get ISH version
This patch adds an API that will fetch the current ISH version from
cbmem. It alerts the user if the current ISH version is outdated.
BUG=b:273661726
Test=The ISHC version, 5.4.2.7779, was retrieved on the Nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 60 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74209/10
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69225 )
Change subject: acpi/acpi.c: Follow spec more closely for MADT
......................................................................
Patch Set 25: Code-Review+1
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Change subject: acpi/acpi.c: Follow spec more closely for MADT
......................................................................
Patch Set 25:
(1 comment)
Patchset:
PS22:
> Maybe it's possible to use an even more generalized code to support P+E cores as done in https://rev […]
Yeah, I think these works should somehow merge together to one solution. We could have the CPU objects (siblings?) linked in the order we want them to appear in MADT instead of using a separate array for the order.
The index in MADT is actually a cross-reference to the processor's ASL Device() with matching UID.
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