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Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h:
https://review.coreboot.org/c/coreboot/+/73392/comment/bca19336_a66f20f8
PS10, Line 8: static const struct pad_config gpio_table[] = {
Add this to a compilation unit rather than a header?
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Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
Patch Set 29:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74005/comment/6bf83cda_3c3dacd1
PS29, Line 1258: if (vboot_recovery_mode_enabled()) {
> At least the check CONFIG(VBOOT) to be combined with vboot_recovery_mode_enabled() since verified boot may not be used in non-chromeOS platforms.
this is not req, please take a look for !VBOOT case https://github.com/coreboot/coreboot/blob/master/src/security/vboot/vboot_c…
```
static inline int vboot_recovery_mode_enabled(void) { return 0; }
```
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Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
Patch Set 29:
(5 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74005/comment/d05d7c10_3d422c52
PS28, Line 1242: fw partition request
> Ack
Looks like you are not honored the comment, but you acknowledged it!
https://review.coreboot.org/c/coreboot/+/74005/comment/6d017009_63f9cdbb
PS28, Line 1250: partition
> Ack
here too...!
https://review.coreboot.org/c/coreboot/+/74005/comment/1d09f739_2cb1318e
PS28, Line 1269: if (id == FPT_PARTITION_NAME_ISHC && !CONFIG(DRIVERS_INTEL_ISH)) {
: printk(BIOS_INFO, "CSE: Info request denied, no ISH partition\n");
: return false;
: }
:
> We could move the check to another location, but I believe it is best to perform all checks before c […]
Agree!
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74005/comment/79242780_f5a2b251
PS29, Line 1258: if (vboot_recovery_mode_enabled()) {
At least the check CONFIG(VBOOT) to be combined with vboot_recovery_mode_enabled() since verified boot may not be used in non-chromeOS platforms.
https://review.coreboot.org/c/coreboot/+/74005/comment/c5f83a87_13d161cf
PS29, Line 1259: nfo request denied, request during recovery mode
nit: I would prefer adding "Skip sending Get Image Info command during recovery mode"!
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Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74335 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
......................................................................
mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Uldren
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335
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Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
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---
M src/mainboard/google/brya/variants/uldren/overridetree.cb
1 file changed, 44 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
John Su: Looks good to me, approved
Ian Feng: Looks good to me, approved
Eric Lai: Looks good to me, approved
Derek Huang: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index dbe46ed..63e14c5 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -25,6 +25,21 @@
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
+ # Configure external V1P05/Vnn/VnnSx Rails
+ register "ext_fivr_settings" = "{
+ .configure_ext_fivr = 1,
+ .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+ .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+ .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+ .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+ .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+ .v1p05_voltage_mv = 1050,
+ .vnn_voltage_mv = 780,
+ .vnn_sx_voltage_mv = 1050,
+ .v1p05_icc_max_ma = 500,
+ .vnn_icc_max_ma = 500,
+ }"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
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Change subject: device: Correct D3Cold Kconfig option
......................................................................
Patch Set 4:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/74328/comment/93eca9a6_12d925d8
PS3, Line 1021: When resuming from S3,
> lost something here?
Meant to delete it - thought I'd waffled on long enough
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Change subject: amdfwtool: Add --fsp-version option
......................................................................
Patch Set 1: -Code-Review
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/74266/comment/3440093e_20ac0952
PS1, Line 214: FSP blobs
> This parameter will be removed, as Paul suggested. […]
oh, so this is mainly a misnomer. fsp is just the fsp-m and fsp-s binary that run on the x86 cores and that coreboot calls into. the parts of the amdfw file are the psp, smu, ... firmwares, abl, and that sort of things, but those aren't part of the fsp
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Change subject: device: Correct D3Cold Kconfig option
......................................................................
Patch Set 3:
(2 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/74328/comment/7dbd3840_8207ff56
PS2, Line 1012: any
> Should be `all` now, right?
Done
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/74328/comment/95f0648b_6313f1eb
PS3, Line 1021: When resuming from S3,
lost something here?
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Change subject: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals
......................................................................
Abandoned
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Change subject: soc/amd/stoneyridge/acpi/northbridge.asl: drop TOM1&TOM2 externals
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> these objects are generated in SSDT via src/soc/amd/common/block/acpi/tables. […]
hmm, cezanne and newer don't have that and even without this, the kernel didn't complain and the decompiled dsdt did have an extern TOM1 declaration
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