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Change subject: src/soc/intel: Document meaning of variables
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71664/comment/3a29b7cd_02ef7bdf
PS1, Line 7: Add in-code documentation
> Maybe: Add descriptions for some technical concepts
Done
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/71664/comment/4dbbef38_4acb7567
PS1, Line 156: DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
> Looks like the file uses C-style comments, most of coreboot uses C-style comments too.
I prefer not adding an entire line for each of these comments. Also its a single line comment, but that is just personal preference.
File src/soc/intel/common/block/include/intelblocks/meminit.h:
https://review.coreboot.org/c/coreboot/+/71664/comment/7b065205_70a47a2a
PS1, Line 26: MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules
> C-style comments
Ack
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71664
to look at the new patch set (#2).
Change subject: src/soc/intel: Document meaning of variables
......................................................................
src/soc/intel: Document meaning of variables
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/common/block/include/intelblocks/meminit.h
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/meteorlake/chip.h
4 files changed, 17 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/71664/2
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Change subject: mb/google/corsola: Add detachable Starmie as variant
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/corsola/display.c:
https://review.coreboot.org/c/coreboot/+/74048/comment/ca329b31_9feb2532
PS9, Line 143: else /* BOARD_GOOGLE_KRABBY_COMMON */
The static assertion above is actually for this. If there is no bridge needed for starmie, please change this to `else if (CONFIG(BOARD_GOOGLE_KRABBY_COMMON))`, and then we can remove the static assertion.
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Change subject: soc/mediatek: Add support for regulator VIO18
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/mt8186/mt6366.c:
https://review.coreboot.org/c/coreboot/+/74341/comment/752c90d3_f5af6c09
PS4, Line 927: case MT6366_VIO18:
Should we assert that `voltage_uv == 1800000`? Please also define a constant marco for `1800000`.
I'd suggest we do the same for `MT6366_VRF12` (in another patch).
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74328 )
Change subject: device: Correct D3Cold Kconfig option
......................................................................
Patch Set 4:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/74328/comment/0f7ed0a1_51e27759
PS2, Line 1007: config D3COLD_SUPPORT
> can we drop the DT option for S0IX then (preferably in another patch)?
We had a discussion about that on IRC today, and it's still ongoing it seems. But in any case, using Kconfig for this is the wrong way I think.
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Change subject: MAINTAINERS: Update maintainers for MediaTek SoCs and mainboards
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74177 )
Change subject: mb/google/myst: Enable iommu
......................................................................
mb/google/myst: Enable iommu
Enable iommu in devicetree for myst in order to allow kernel to load and
initialize IOMMU.
Bug=b:276805280
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74177
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 7980101..d3b06b9 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/phoenix
device domain 0 on
+ device ref iommu on end
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 alias chrome_ec on end
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74103 )
Change subject: mb/google/myst: Enable console UART
......................................................................
mb/google/myst: Enable console UART
Enable the console UART for myst devices.
Bug=b:275900837
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I52c1b86c46907216d88f98917968b833af0d5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74103
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---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
2 files changed, 22 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Tim Van Patten: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig
index 0305e25..353f23c 100644
--- a/src/mainboard/google/myst/Kconfig
+++ b/src/mainboard/google/myst/Kconfig
@@ -7,6 +7,7 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
+ select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index ef41b0d..7980101 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -7,4 +7,5 @@
end
end
end # domain
+ device ref uart_0 on end # UART0
end # chip soc/amd/phoenix
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