coreboot-gerrit April 2023

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Arthur Heymans (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Simon Chou. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 33: (1 comment) File src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h: https://review.coreboot.org/c/coreboot/+/71968/comment/56fa3d69_3b0a4301 PS22, Line 41: static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = { : /* DMI port: array index 0 */ : CFG_UPD_PCIE_PORT(0, 0, 0), : /* IOU0 (PE0): array index 1 ~ 8 */ : CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : /* IOU1 (PE1): array index 9 ~ 16 */ : CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : /* IOU2 (PE2): array index 17 ~ 24 */ : CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(1, 0, 0), : /* IOU3 (PE3): array index 25 ~ 32 */ : CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 27), /* 48:03.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 29), /* 48:05.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 31), /* 48:07.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : /* IOU4 (PE4): array index 33 ~ 40 */ : CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 35), /* 59:03.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */ : CFG_UPD_PCIE_PORT(1, 0, 0), : /* ArcherCity doesn't use IOU5 ~ IOU6. */ : } Don't define variables in headers. -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 33 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:48:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD
by Lean Sheng Tan (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Christian Walter, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74339 ) Change subject: soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Gerrit-Change-Number: 74339 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:46:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 12 Apr '23

12 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74359 ) Change subject: AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/southbridge/amd/pi/hudson/Kconfig 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74359/1 diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index e139639..5cf275b 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -6,20 +6,8 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* TODO: Remove the hardcode */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - return current; } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 4b19431..6a3d61d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -10,7 +10,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_CUSTOM_MADT select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE -- To view, visit https://review.coreboot.org/c/coreboot/+/74359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a Gerrit-Change-Number: 74359 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 12 Apr '23

12 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74358 ) Change subject: soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC For the first IOAPIC, use the common MADT generator with default IRQ overrides. Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 20 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74358/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 8f4e308..c750e7e 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -1,7 +1,9 @@ config SOC_INTEL_COMMON_BLOCK_ACPI depends on SOC_INTEL_COMMON_BLOCK_CPU depends on SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + select ACPI_CUSTOM_MADT bool help Intel Processor common code for ACPI diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f692b41..81d1371 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -80,12 +80,12 @@ /* IOAPIC */ ioapic_entries = soc_get_ioapic_info(&ioapic_table); - for (int i = 0; i < ioapic_entries; i++) - current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - current += acpi_create_madt_sci_override((void *)current); + /* Default SOC IOAPIC entry */ + ASSERT(ioapic_table[0] == IO_APIC_ADDR); + + for (int i = 1; i < ioapic_entries; i++) + current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Gerrit-Change-Number: 74358 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Lean Sheng Tan (Code Review) 12 Apr '23

12 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... mb/intel: Add 2 SPR sockets CRB Archer City Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. The multisocket support depends on Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190 Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71968 Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 487 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Johnny Lin: Looks good to me, approved diff --git a/src/mainboard/intel/archercity_crb/Kconfig b/src/mainboard/intel/archercity_crb/Kconfig new file mode 100644 index 0000000..656d366 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/Kconfig @@ -0,0 +1,34 @@ +if BOARD_INTEL_ARCHERCITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select CONSOLE_OVERRIDE_LOGLEVEL + select IPMI_KCS + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SAPPHIRERAPIDS_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select MAINBOARD_USES_IFD_GBE_REGION + select VPD + select OCP_VPD + +config MAINBOARD_DIR + string + default "intel/archercity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Archer City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_SOCKET + int + default 2 + +endif diff --git a/src/mainboard/intel/archercity_crb/Kconfig.name b/src/mainboard/intel/archercity_crb/Kconfig.name new file mode 100644 index 0000000..18dee3a --- /dev/null +++ b/src/mainboard/intel/archercity_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ARCHERCITY_CRB + bool "Archer City CRB" diff --git a/src/mainboard/intel/archercity_crb/Makefile.inc b/src/mainboard/intel/archercity_crb/Makefile.inc new file mode 100644 index 0000000..0688aa1 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/archercity_crb/acpi/platform.asl b/src/mainboard/intel/archercity_crb/acpi/platform.asl new file mode 100644 index 0000000..4853874 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/acpi/platform.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <southbridge/intel/common/acpi/sleepstates.asl> + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/intel/archercity_crb/board.fmd b/src/mainboard/intel/archercity_crb/board.fmd new file mode 100644 index 0000000..92831e7 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/board.fmd @@ -0,0 +1,13 @@ +FLASH 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fed000 + SI_PT@0x2ff0000 0x10000 + } + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/intel/archercity_crb/board_info.txt b/src/mainboard/intel/archercity_crb/board_info.txt new file mode 100644 index 0000000..3a3a446 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Archer City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/archercity_crb/bootblock.c b/src/mainboard/intel/archercity_crb/bootblock.c new file mode 100644 index 0000000..b781b6b --- /dev/null +++ b/src/mainboard/intel/archercity_crb/bootblock.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +void bootblock_mainboard_early_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For ArcherCity CRB, only SUART1 is used. + */ + uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); + + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/intel/archercity_crb/devicetree.cb b/src/mainboard/intel/archercity_crb/devicetree.cb new file mode 100644 index 0000000..66a08a9 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/devicetree.cb @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + register "turbo_ratio_limit" = "0x181819191e242424" + register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18" + + device domain 0 on + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + end +end diff --git a/src/mainboard/intel/archercity_crb/dsdt.asl b/src/mainboard/intel/archercity_crb/dsdt.asl new file mode 100644 index 0000000..2204748 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // SPR-SP ACPI tables + #include <soc/intel/xeon_sp/spr/acpi/uncore.asl> + + // LPC related entries + Scope (\_SB.PC00) + { + #include <soc/intel/xeon_sp/spr/acpi/pch.asl> + } +} diff --git a/src/mainboard/intel/archercity_crb/include/mainboard_ras.h b/src/mainboard/intel/archercity_crb/include/mainboard_ras.h new file mode 100644 index 0000000..76f3872 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/include/mainboard_ras.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_RAS_H +#define MAINBOARD_RAS_H + +struct fru { + const char *str; +}; + +struct fru *mainboard_ras_get_ch_map(void); + +#endif diff --git a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h b/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h new file mode 100644 index 0000000..2dcf6c9 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SPRSP_AC_IIO_H_ +#define _SPRSP_AC_IIO_H_ + +#include <defs_iio.h> + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = 0, \ + .SLOTHPSUP = 0, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = 1, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = 0, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + .PcieMaxPayload = 0x7, \ + .PciePortLinkSpeed = 0, \ + .DfxDnTxPresetGen3 = 0xFF \ + } + +/* + * Standard ArcherCity IIO PCIe Port Table + */ +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 27), /* 48:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 29), /* 48:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 31), /* 48:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 35), /* 59:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* ArcherCity doesn't use IOU5 ~ IOU6. */ +}; + +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 97:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 9), /* a7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* b7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* c7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 27), /* c7:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 29), /* c7:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 31), /* c7:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* d7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 35), /* d7:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 37), /* d7:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* ArcherCity doesn't use IOU5 ~ IOU6. */ +}; +#endif /* _SPRSP_CL_IIO_H_ */ diff --git a/src/mainboard/intel/archercity_crb/ramstage.c b/src/mainboard/intel/archercity_crb/ramstage.c new file mode 100644 index 0000000..38bf576 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/ramstage.c @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c new file mode 100644 index 0000000..68025b4 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include <soc/romstage.h> +#include <defs_cxl.h> +#include <defs_iio.h> +#include <sprsp_ac_iio.h> + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + int port; + + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = + (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + + /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ + for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) { + PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP; + PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP; + PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable; + PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE; + PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload; + PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed; + PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3; + } + /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) { + PciePortConfig[0].PEXPHIDE[port] = 1; + PciePortConfig[0].HidePEXPMenu[port] = 1; + } + PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + PciePortConfig[0].PcieGlobalAspm = 0x1; + PciePortConfig[0].PcieMaxReadRequestSize = 0x5; + + /* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ + for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) { + PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP; + PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP; + PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable; + PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE; + PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload; + PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed; + PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3; + } + /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) { + PciePortConfig[1].PEXPHIDE[port] = 1; + PciePortConfig[1].HidePEXPMenu[port] = 1; + } + PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + PciePortConfig[1].PcieGlobalAspm = 0x1; + PciePortConfig[1].PcieMaxReadRequestSize = 0x5; + + /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ + if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { + printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); + } else { + /* Set socket 0 IIO PCIe PE1 to CXL mode */ + /* Set socket 1 IIO PCIe PE0 to CXL mode */ + /* eg. Protocl Auto Negotiation */ + mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL; + mupd->FspmConfig.IioPcieSubSystemMode0[1] = IIO_MODE_CXL; + + mupd->FspmConfig.DfxCxlHeaderBypass = 0; + mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; + + mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */ + } +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + uint8_t val; + + /* Send FSP log message to SOL */ + if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) + mupd->FspmConfig.SerialIoUartDebugEnable = val; + else { + printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", + FSP_LOG, FSP_LOG_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + } + + /* Set Rank Margin Tool to disable. */ + mupd->FspmConfig.EnableRMT = 0x0; + /* Enable - Portions of memory reference code will be skipped + * when possible to increase boot speed on warm boots. + * Disable - Disables this feature. + * Auto - Sets it to the MRC default setting. + */ + mupd->FspmConfig.AttemptFastBoot = 0x1; + mupd->FspmConfig.AttemptFastBootCold = 0x1; + + /* Set Adv MemTest Option to 0. */ + mupd->FspmConfig.AdvMemTestOptions = 0x0; + /* Set MRC Promote Warnings to disable. + Determines if MRC warnings are promoted to system level. */ + mupd->FspmConfig.promoteMrcWarnings = 0x0; + /* Set Promote Warnings to disable. + Determines if warnings are promoted to system level. */ + mupd->FspmConfig.promoteWarnings = 0x0; + + mainboard_config_iio(mupd); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 33 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Lean Sheng Tan (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Juan Sanchez, Shelly Chang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 32 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:42:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Lean Sheng Tan (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Juan Sanchez, Shelly Chang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 32: (1 comment) Patchset: PS32: I see no further concern regarding current patch, it will be a learning curve for everyone, but still welcome to coreboot and Thank You for contributing and working together to make the code in good quality :) Good job everyone! -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 32 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD CnviWifiCore
by Subrata Banik (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Paul Menzel, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74306 ) Change subject: soc/intel/meteorlake: Hook up UPD CnviWifiCore ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Gerrit-Change-Number: 74306 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:03:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Replace assert with error message
by Subrata Banik (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74370 ) Change subject: soc/intel/meteorlake: Replace assert with error message ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/74370/comment/bf514f35_237a88f3 PS2, Line 563: /* CNVi */ we don't kw the default DSC value of CnviWifiCore/CnviBtCore/CnviBtAudioOffload hence, in case `s_cfg->CnviMode=0`, i would consider resetting (0) those UPDs. Additionally, CnviBtAudioOffload can be only set if CnviBtCore is enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/74370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 Gerrit-Change-Number: 74370 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 11:03:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Replace assert with error message
by Kapil Porwal (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74370 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Replace assert with error message ...................................................................... soc/intel/meteorlake: Replace assert with error message Avoid asserts related to CNVi UPDs which are not boot critical. Instead, add error messages which are more helpful in identifying the issue. BUG=none TEST=Boot to the OS on google/rex Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74370/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 Gerrit-Change-Number: 74370 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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