Attention is currently required from: Tarun Tuli, Dinesh Gehlot.
Hello build bot (Jenkins), Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74208
to look at the new patch set (#15).
Change subject: soc/intel/: Store ISH firmware version into cbmem table
......................................................................
soc/intel/: Store ISH firmware version into cbmem table
The patch stores the ISH in the CBMEM table. It verifies CSE has been
updated by comparing previous and current CSE versions. If it has, the
patch updates the previous CSE version with the current CSE version. It
then updates the CBMEM table with the current ISH version.
BUG=b:273661726
Test=The current and old cse and ish versions are verified on the nissa
during cold and warm reboots. Additionally, version updates are verified
by a debug patch that purposely updated the stored cse version.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 70 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/15
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Gerrit-Change-Number: 74208
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74309 )
Change subject: payloads/external/Makefile.inc: Make linuxboot a phony target
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > What is the reason behind this? […]
Thanks. Could you add this reason to the commit message?
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Attention is currently required from: Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman.
Hello build bot (Jenkins), SRIDHAR SIRICILLA, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Paul Menzel, Kapil Porwal, Rizwan Qureshi, Reka Norman, Sridhar Siricilla, Meera Ravindranath,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74005
to look at the new patch set (#29).
Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
soc/intel/cmd/block: Implement an API to get firmware partition details
This patch retrieves details of a specified firmware partition table.
The information retrieved includes the current firmware version and
other information about the firmware partition. The patch communicates
with the ME using the HECI command to acquire this information.
BUG=b:273661726
Test=Verified the changes for ISH partition on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/29
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Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot.
Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Sridhar Siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74256
to look at the new patch set (#11).
Change subject: soc/intel/: Store CSE firmware version into cbmem table
......................................................................
soc/intel/: Store CSE firmware version into cbmem table
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called either from RAMSTAGE or ROMSTAGE
based on underlying platform.
BUG=b:273661726
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
5 files changed, 80 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/11
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74309 )
Change subject: payloads/external/Makefile.inc: Make linuxboot a phony target
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> What is the reason behind this?
If a file or directory called linuxboot exists then this target is broken. As this target generates no file 'called' linuxboot is should be phony.
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Change subject: payloads/external/Makefile.inc: Make linuxboot a phony target
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
What is the reason behind this?
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Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70270 )
Change subject: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW
......................................................................
Abandoned
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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74296/comment/b0318ec9_9353f4ab
PS5, Line 14: only 1.4Gi,
: after the fix it's showing the expected total memory size 15Gi
just saying.. a 10x error is not "very small error" though :D
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Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
its quite weird that you +1 your own patch :P
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