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Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
Patch Set 32:
(2 comments)
File src/mainboard/google/myst/Kconfig:
https://review.coreboot.org/c/coreboot/+/74111/comment/6d65cadb_7380576d
PS32, Line 23: SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
This requires PSP support to assume ownership of the bus. Probably have to wait until the board is powered on.
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74111/comment/7d8f1fa7_4b065e52
PS32, Line 54: static void configure_psp_tpm_gpio(void)
This needs to wait until PSP assumes ownership of the bus.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek: Add support for regulator VIO18
......................................................................
soc/mediatek: Add support for regulator VIO18
To provide power to MIPI panel STA_HIMAX83102_J02, add support for
regulator VIO18.
BUG=b:272425116
TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie.
Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5
Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com>
---
M src/soc/mediatek/common/include/soc/regulator.h
M src/soc/mediatek/mt8186/include/soc/mt6366.h
M src/soc/mediatek/mt8186/mt6366.c
3 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74341/7
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Change subject: mb/google/corsola: Add detachable Starmie as variant
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/corsola/display.c:
https://review.coreboot.org/c/coreboot/+/74048/comment/3d755ab9_b5faf2b7
PS10, Line 143: bridge->power_on
> I agree we should use `if` instead of `assert` since the patch should be verified before submitting. […]
Done. thank you.
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Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74303 )
Change subject: soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
......................................................................
soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
Use the common acpi_fill_root_complex_tom function instead of the SoC-
level northbridge_fill_ssdt_generator function that does basically the
same.
TEST=Resulting coreboot SSDT remains unchanged on Careena.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74303
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/stoneyridge/northbridge.c
1 file changed, 22 insertions(+), 22 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 7913827..b1d2bdd 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
+#include <amdblocks/acpi.h>
#include <amdblocks/biosram.h>
#include <amdblocks/hda.h>
#include <device/pci_ops.h>
@@ -186,27 +187,6 @@
return (unsigned long)current;
}
-static void northbridge_fill_ssdt_generator(const struct device *device)
-{
- msr_t msr;
- char pscope[] = "\\_SB.PCI0";
-
- acpigen_write_scope(pscope);
- msr = rdmsr(TOP_MEM);
- acpigen_write_name_dword("TOM1", msr.lo);
- msr = rdmsr(TOP_MEM2);
- /*
- * Since XP only implements parts of ACPI 2.0, we can't use a qword
- * here.
- * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
- * slide 22ff.
- * Shift value right by 20 bit to make it fit into 32bit,
- * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
- */
- acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
- acpigen_pop_len();
-}
-
static unsigned long agesa_write_acpi_tables(const struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@@ -285,7 +265,7 @@
.set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
- .acpi_fill_ssdt = northbridge_fill_ssdt_generator,
+ .acpi_fill_ssdt = acpi_fill_root_complex_tom,
.write_acpi_tables = agesa_write_acpi_tables,
};
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Change subject: mb/google/corsola: Add detachable Starmie as variant
......................................................................
mb/google/corsola: Add detachable Starmie as variant
The 'Starmie' is a mt8186 detachable reference design that will share
most of Corsola design. For AP firmware, there will be a few changes,
mostly in display (MIPI interface and w/o bridge), so we create it
as a variant in Corsola.
BUG=b:275470328
BRANCH=corsola
TEST=./util/abuild/abuild -t google/corsola -b starmie -a
Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a
Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/corsola/Kconfig.name
M src/mainboard/google/corsola/display.c
3 files changed, 36 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74048/12
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Change subject: mb/google/myst: Add initial fch irq routing
......................................................................
Patch Set 29:
(1 comment)
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74109/comment/2dc102d6_815d7d44
PS29, Line 12: accessed via I/O ports 0xc00/0xc01. */
Can you please cite the source for the routing table?
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Change subject: mb/google/myst: Enable crypto in devicetree
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74275/comment/c5330b80_3f980755
PS9, Line 7: nable PSP in devicetree
> The commit message is not accurately defining what is enabled here. […]
Done
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Change subject: mb/google/myst: Enable crypto in devicetree
......................................................................
mb/google/myst: Enable crypto in devicetree
Add the crypto device to the devicetree.
BUG=b:277214359
TEST=builds
Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74275/10
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