coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by cong yang (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Ruihai Zhou, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74341 to look at the new patch set (#6). Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... soc/mediatek: Add support for regulator VIO18 To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/regulator.h M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 3 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74341/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 6 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/corsola: Add detachable Starmie as variant
by Ruihai Zhou (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74048 ) Change subject: mb/google/corsola: Add detachable Starmie as variant ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/corsola/display.c: https://review.coreboot.org/c/coreboot/+/74048/comment/2572928b_b376b728 PS10, Line 143: bridge->power_on > Sounds good. but it seems that the callback `bridge_ps8640_post_power_on` isn't required, can we switch assert to if and remove the unnecessary callback? -- To view, visit https://review.coreboot.org/c/coreboot/+/74048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Gerrit-Change-Number: 74048 Gerrit-PatchSet: 11 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 03:02:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add initial I2C configuration
by Eric Lai (Code Review) 13 Apr '23

13 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74108 ) ( 27 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Add initial I2C configuration ...................................................................... mb/google/myst: Add initial I2C configuration Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:275939564 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74108 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/variants/baseboard/devicetree.cb 2 files changed, 62 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 8405e8a..956267f 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -9,6 +9,8 @@ def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select ELOG diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index e542817..fbc9e93 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,5 +1,40 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/phoenix + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB + + # I2C Config + #+-------------------+----------------------------+ + #| Field | Value | + #+-------------------+----------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | GSC TPM | + #| I2C3 | Speaker, Codec, P-SAR, USB | + #+-------------------+----------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + }" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) @@ -111,4 +146,8 @@ end end # domain device ref uart_0 on end # UART0 + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end end # chip soc/amd/phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/74108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a Gerrit-Change-Number: 74108 Gerrit-PatchSet: 30 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by cong yang (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Yidi Lin. cong yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74341 ) Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/74341/comment/f3561394_51e1df26 PS4, Line 927: case MT6366_VIO18: > Should we assert that `voltage_uv == 1800000`? Please also define a constant marco for `1800000`. […] 1800000 seems to be used in several places in this file, and there are some 2900000/3000000/3300000, do you need to change all 1800000 to macro definitions? -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 5 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 03:00:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/corsola: Add detachable Starmie as variant
by Yidi Lin (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74048 ) Change subject: mb/google/corsola: Add detachable Starmie as variant ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/corsola/display.c: https://review.coreboot.org/c/coreboot/+/74048/comment/d4367da5_11eefec8 PS10, Line 143: bridge->power_on > If all callbacks are required, can we check only `if (!bridge)`, and then use assertions for the cal […] Sounds good. -- To view, visit https://review.coreboot.org/c/coreboot/+/74048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Gerrit-Change-Number: 74048 Gerrit-PatchSet: 11 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 02:59:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable elog
by Eric Lai (Code Review) 13 Apr '23

13 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74282 ) Change subject: mb/google/myst: Enable elog ...................................................................... mb/google/myst: Enable elog Enable ELOG for Myst. BUG=b:275938975 TEST=builds Change-Id: I214e2dbaa3bc40c3f4ca68c8ee4b1398446d7090 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74282 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 353f23c..8405e8a 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -11,6 +11,8 @@ select BOARD_ROMSIZE_KB_16384 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI + select ELOG + select ELOG_GSMI select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select MAINBOARD_HAS_CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/74282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214e2dbaa3bc40c3f4ca68c8ee4b1398446d7090 Gerrit-Change-Number: 74282 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Add ACPI configuration for USB ports
by Eric Lai (Code Review) 13 Apr '23

13 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74106 ) Change subject: mb/google/myst: Add ACPI configuration for USB ports ...................................................................... mb/google/myst: Add ACPI configuration for USB ports The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74106 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 123 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 5bb1e8c..e542817 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -3,12 +3,105 @@ device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) - device ref xhci_0 on end - device ref xhci_1 on end + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""World-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)" + register "enable_delay_ms" = "500" + register "enable_off_delay_ms" = "200" + register "use_gpio_for_status" = "true" + device ref usb2_port4 on end + end + end + end + end end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - device ref usb4_xhci_0 on end - device ref usb4_xhci_1 on end + device ref usb4_xhci_0 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref usb4_xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port6 on end + end + end + end + end + device ref usb4_xhci_1 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref usb4_xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port7 on end + end + end + end + end end device ref iommu on end device ref lpc_bridge on -- To view, visit https://review.coreboot.org/c/coreboot/+/74106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Gerrit-Change-Number: 74106 Gerrit-PatchSet: 28 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Enable XHCI controllers
by Eric Lai (Code Review) 13 Apr '23

13 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74105 ) Change subject: mb/google/myst: Enable XHCI controllers ...................................................................... mb/google/myst: Enable XHCI controllers Enable the XHCI controllers in the devicetree for myst project. BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74105 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 2a1c2d2..5bb1e8c 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -3,6 +3,12 @@ device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on end + device ref xhci_1 on end + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref usb4_xhci_0 on end + device ref usb4_xhci_1 on end end device ref iommu on end device ref lpc_bridge on -- To view, visit https://review.coreboot.org/c/coreboot/+/74105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Gerrit-Change-Number: 74105 Gerrit-PatchSet: 27 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Enable internal graphics
by Eric Lai (Code Review) 13 Apr '23

13 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74104 ) Change subject: mb/google/myst: Enable internal graphics ...................................................................... mb/google/myst: Enable internal graphics Enable internal graphics on the phoenix soc for myst projects. BUG=b:275900162 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74104 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index d3b06b9..2a1c2d2 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,6 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/phoenix device domain 0 on + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + end device ref iommu on end device ref lpc_bridge on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/74104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Gerrit-Change-Number: 74104 Gerrit-PatchSet: 27 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by Yu-Ping Wu (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74341 ) Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/74341/comment/17939c5f_c4dc1140 PS5, Line 795: static void pmic_set_vio18_vol(voltage_uv) Missing `u32`. -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 5 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 02:56:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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