coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by Yu-Ping Wu (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74341 ) Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/74341/comment/d915abc5_bcd9db92 PS7, Line 797: voltage_uv > OK,thanks. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 8 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:39:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by Yidi Lin (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74341 ) Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... Patch Set 8: Code-Review+1 (2 comments) Patchset: PS8: Could you also submit a patch for MT6366_VRF12 and rebase whole patchset (including CB:74342) ? File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/74341/comment/0fcfb966_9d9e5ed2 PS7, Line 797: voltage_uv > OK,thanks. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 8 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/corsola: Add detachable Starmie as variant
by Yu-Ping Wu (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Ruihai Zhou. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74048 ) Change subject: mb/google/corsola: Add detachable Starmie as variant ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Gerrit-Change-Number: 74048 Gerrit-PatchSet: 12 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:38:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: screebo: initial coreboot for rex variant
by build bot (Jenkins) (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74392 ) Change subject: screebo: initial coreboot for rex variant ...................................................................... Patch Set 1: (12 comments) File src/mainboard/google/rex/variants/screebo/fw_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/13db1bd5_36578aa4 PS1, Line 47: // printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/5b959a51_99a1cbdd PS1, Line 48: // GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/9e83d32b_50c65b60 PS1, Line 49: // GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/86a33732_d5d114f8 PS1, Line 50: // GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/0fea3b76_bc08c291 PS1, Line 52: // printk(BIOS_INFO, "Configure GPIOs for SoundWire audio.\n"); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/e8b5f478_28c5fe99 PS1, Line 53: // GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/5d2d4d07_34366c0d PS1, Line 55: // printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/f2085051_86dff063 PS1, Line 56: // GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); please, no space before tabs File src/mainboard/google/rex/variants/screebo/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/f2b821a3_eaa420f1 PS1, Line 17: // if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/ced40dc3_4375abe8 PS1, Line 18: // acpigen_soc_clear_tx_gpio(GPP_B09); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/db1e5617_030b0bb1 PS1, Line 20: // if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174086): https://review.coreboot.org/c/coreboot/+/74392/comment/f25baf62_aa73135c PS1, Line 21: // acpigen_soc_set_tx_gpio(GPP_B09); please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/74392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6fe30ebbabb4325b8c855ec0fb6eaf7bc2e8ee Gerrit-Change-Number: 74392 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/rex: Create screebo variant
by build bot (Jenkins) (Code Review) 13 Apr '23

13 Apr '23

1 0

[L] Change in coreboot[master]: screebo: initial coreboot for rex variant
by Simon Zhou (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Simon Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74392 ) Change subject: screebo: initial coreboot for rex variant ...................................................................... screebo: initial coreboot for rex variant TEST=emerge-rex coreboot BUG=b:27681495 Change-Id: I0a6fe30ebbabb4325b8c855ec0fb6eaf7bc2e8ee --- A src/mainboard/google/rex/variants/screebo/Makefile.inc A src/mainboard/google/rex/variants/screebo/fw_config.c A src/mainboard/google/rex/variants/screebo/gpio.c A src/mainboard/google/rex/variants/screebo/variant.c 4 files changed, 541 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/74392/1 diff --git a/src/mainboard/google/rex/variants/screebo/Makefile.inc b/src/mainboard/google/rex/variants/screebo/Makefile.inc new file mode 100644 index 0000000..cdbf407 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/rex/variants/screebo/fw_config.c b/src/mainboard/google/rex/variants/screebo/fw_config.c new file mode 100644 index 0000000..aef2217 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/fw_config.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, DN_20K), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + return; + } + + // if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + // printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); + // GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + // GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); + // GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + // } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98363_CS42L42_SNDW))) { + // printk(BIOS_INFO, "Configure GPIOs for SoundWire audio.\n"); + // GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + // } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + // printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); + // GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + // } +} diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c new file mode 100644 index 0000000..5a854ba --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -0,0 +1,443 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: 3EC4CE58201758F4 + * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <console/console.h> +#include <boardid.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 : [] ==> EN_UCAM_PWR */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */ + PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG), + /* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A14, 1, DEEP), + /* GPP_A15 : [] ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */ + /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), + + /* GPP_A18 : [] ==> CAM_PSW_L */ + PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), + /* GPP_A21 : [] ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_A21, NONE, DEEP), + + /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_B01 : [] ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_B01, 1, DEEP), + /* GPP_B02 : net NC is not present in the given design */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03 : net NC is not present in the given design */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05 : [] ==> SPKR_INT_L_R */ + PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B06 : [] ==> HP_INT_L_R */ + PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), + /* GPP_B07 : [] ==> RST_HP_L */ + PAD_CFG_GPO(GPP_B07, 1, DEEP), + /* GPP_B08 : net NC is not present in the given design */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09 : [] ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 : [] ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_B11, 1, LOCK_CONFIG), + /* GPP_B12 : [] ==> SLP_SO_R_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 : [] ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15 : [] ==> USB_OC3# */ + PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* GPP_B17 : [] ==> EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), + /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ + PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), + /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ + PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), + /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 : [] ==> WWAN_CONFIG0 */ + PAD_CFG_GPI_LOCK(GPP_B23, NONE, LOCK_CONFIG), + + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 0, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), + /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO_LOCK(GPP_C03, 0, LOCK_CONFIG), + /* GPP_C04 : [] ==> EN_WCAM_PWR */ + PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ + PAD_CFG_GPO(GPP_C05, 1, PLTRST), + /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_C06, 0, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), + /* GPP_C08 : [] ==> SOCHOT_ODL */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), + /* GPP_C09 : net NC is not present in the given design */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10 : net NC is not present in the given design */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 : [] ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13 : [] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* GPP_C16 : [] ==> USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 : [] ==> USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 : [] ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF6), + /* GPP_C19 : [] ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF6), + /* GPP_C20 : [] ==> USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21 : [] ==> USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22 : [] ==> SOC_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_C22, 0, LOCK_CONFIG), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_C23, 1, LOCK_CONFIG), + + /* GPP_D00 : WCAM_MCLK_R */ + PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), + /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), + /* GPP_D04 : [] ==> EN_SPKR */ + PAD_CFG_GPO(GPP_D04, 1, DEEP), + /* GPP_D05 : net NC. Test pad. */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06 : net NC. Test pad.*/ + PAD_NC(GPP_D06, NONE), + /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL */ + PAD_CFG_GPO_LOCK(GPP_D07, 1, LOCK_CONFIG), + /* GPP_D08 : net NC. Test pad. */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09 : [] ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), + /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), + /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* GPP_D18 : net NC is not present in the given design */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 : net NC is not present in the given design */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20 : net NC is not present in the given design */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 : net NC is not present in the given design */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 : net NC is not present in the given design */ + PAD_NC(GPP_D23, NONE), + + /* GPP_E00 : [] ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC(GPP_E00, NONE, PLTRST, LEVEL, NONE), + /* GPP_E01 : MEM_STRAP_2 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), + /* GPP_E02 : MEM_STRAP_1 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E04 : [] ==> HPS_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, NONE), + /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : [] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_E08 : [] ==> SAR2_INT_L */ + PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, NONE, LOCK_CONFIG), + /* GPP_E09 : No heuristic was found useful */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), + /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E10, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E11 : [] ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* GPP_E12 : [] ==> MEM_STRAP_3 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 : net NC is not present in the given design */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16 : net NC. Test pad. */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17 : [] ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* GPP_E22 : [] ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + + /* GPP_F00 : [] ==> CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 : [] ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 : [] ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 : [] ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 : [] ==> CNV_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 : [] ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07 : [] ==> UCAM_MCLK_R */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + /* GPP_F08 : [] ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT), + /* GPP_F10 : [] ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F10, NONE, PLTRST, LEVEL, INVERT), + /* GPP_F11 : GSP1_SOC_CLK_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5), + /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), + /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), + /* GPP_F14 : GSPI0_SOC_DO_TCHSCR_DI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15 : [] ==> GSPI0_SOC_DI_TCHSCR_DO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16 : [] ==> GSPI0_SOC_TCHSCR_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), + /* GPP_F18 : [] ==> GSPI0_SOC_TCHSCR_CS_L */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), + /* GPP_F19 : [] ==> GPP_F19_STRAP */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 : [] ==> GPP_F20_STRAP */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 : [] ==> GPP_F21_STRAP */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 : net NC is not present in the given design */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 : net NC is not present in the given design */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), + /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), + /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ + PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), + /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ + PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + /* GPP_H11 : net NC is not present in the given design */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13 : [] ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : [] ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ + PAD_CFG_GPO(GPP_H15, 0, PLTRST), + /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00 : [] ==> SDW_HP_CLK */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01 : [] ==> SDW_HP_DATA */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02 : [] ==> DMIC_SOC_CLK0_DB_RC */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), + /* GPP_S03 : [] ==> DMIC_SOC_DATA0_DB_R */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), + /* GPP_S04 : [] ==> SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1), + /* GPP_S05 : [] ==> SDW_SPKR_DATA */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1), + /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* GPP_V00 : [] ==> BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01 : [] ==> ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04 : [] ==> SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 : [] ==> SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 : [] ==> SOC_SLP_A_L */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V08 : [] ==> SOC_SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 : [] ==> SLP_S5_L */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/ + PAD_NC(GPP_V11, NONE), + /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V14 : [] ==> SOC_WAKE_L */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V22 : [] ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + /* GPP_V23 : [] ==> UCAM_RST_L */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B17 : [] ==> EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP (updated in ramstage) */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_A15 : [] ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + + /* GPP_E07 : [] ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D03, 1, DEEP), + + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + /* GPP_E07 : [] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c new file mode 100644 index 0000000..e8ac782 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <fw_config.h> +#include <sar.h> +#include <variant/gpio.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + // if (entry == S0IX_ENTRY) { + // if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) + // acpigen_soc_clear_tx_gpio(GPP_B09); + // } else if (entry == S0IX_EXIT) { + // if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) + // acpigen_soc_set_tx_gpio(GPP_B09); + // } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6fe30ebbabb4325b8c855ec0fb6eaf7bc2e8ee Gerrit-Change-Number: 74392 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/rex: Create screebo variant
by Simon Zhou (Code Review) 13 Apr '23

13 Apr '23

Simon Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74391 ) Change subject: mb/google/rex: Create screebo variant ...................................................................... mb/google/rex: Create screebo variant Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/screebo/include/variant/ec.h A src/mainboard/google/rex/variants/screebo/include/variant/gpio.h A src/mainboard/google/rex/variants/screebo/memory/Makefile.inc A src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/screebo/overridetree.cb 8 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74391/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 6cea7fc..62ece95 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -80,10 +80,12 @@ config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 + default "Screebo" if BOARD_GOOGLE_SCREEBO config VARIANT_DIR string default "rex0" if BOARD_GOOGLE_REX0 + default "screebo" if BOARD_GOOGLE_SCREEBO config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index ca63842..886a2f0 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -4,3 +4,7 @@ bool "-> Rex 0" select BOARD_GOOGLE_BASEBOARD_REX select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_SCREEBO + bool "-> Screebo" + select BOARD_GOOGLE_BASEBOARD_REX diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/ec.h b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb new file mode 100644 index 0000000..6c284b3 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/meteorlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/74391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Gerrit-Change-Number: 74391 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by cong yang (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. cong yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74341 ) Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... Patch Set 8: (2 comments) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/74341/comment/70f3b892_535fa8cb PS7, Line 17: #define VIO18_VOLTAGE_UV 1800000 > Move to line 792. Done https://review.coreboot.org/c/coreboot/+/74341/comment/d7f62f56_38d0e87d PS7, Line 797: voltage_uv > what about `vio18_uv` ? OK,thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 8 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:33:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VIO18
by cong yang (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Ruihai Zhou, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74341 to look at the new patch set (#8). Change subject: soc/mediatek: Add support for regulator VIO18 ...................................................................... soc/mediatek: Add support for regulator VIO18 To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/regulator.h M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74341/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/74341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Gerrit-Change-Number: 74341 Gerrit-PatchSet: 8 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Karthik Ramasubramanian (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/60c51e75_91a5b127 PS4, Line 218: if (!CONFIG_CBFS_CACHE_SIZE) > I suggest updating this to: […] By extra copy into the cache, are you referring to cbfs_cache? -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 06:25:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023