coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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5761 discussions

[S] Change in coreboot[master]: soc/mediatek: Add assert for regulator VRF12
by cong yang (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Ruihai Zhou, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74394 to look at the new patch set (#2). Change subject: soc/mediatek: Add assert for regulator VRF12 ...................................................................... soc/mediatek: Add assert for regulator VRF12 Add assert for MT6366_VRF12, define a constant macro for 1200000. BUG=none TEST=build board starmie with mt8186. Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/74394/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Gerrit-Change-Number: 74394 Gerrit-PatchSet: 2 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/efi: Fix linker error when SMM phase uses option API
by Lean Sheng Tan (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Benjamin Doron, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73905 ) Change subject: drivers/efi: Fix linker error when SMM phase uses option API ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3b52965d8fde141c12266a716f254dd45559d5 Gerrit-Change-Number: 73905 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:57:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
by Lean Sheng Tan (Code Review) 13 Apr '23

13 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74296 ) Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled ...................................................................... soc/intel/xeon_sp: Fix very small total memory when CXL is enabled Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10 Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 54 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 5249a94..3744359 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -249,10 +249,16 @@ if (CONFIG(SOC_INTEL_HAS_CXL)) { /* 4GiB -> CXL Memory */ uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); - - res = reserved_ram_from_to(dev, index++, 0x100000000, - mc_values[TOHM_REG] - (uint64_t)gi_mem_size + 1); + gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ + /* + * Memory layout when there is CXL HDM (Host-managed Device Memory): + * -------------- <- TOHM + * CXL memory regions (pds global variable records the base/size of them) + * Processor attached high memory + * -------------- <- 0x100000000 (4GB) + */ + res = upper_ram_end(dev, index++, + mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); LOG_RESOURCE("high_ram", dev, res); /* CXL Memory */ @@ -269,8 +275,9 @@ else flags |= IORESOURCE_STORED; - res = fixed_mem_range_flags(dev, index++, (uint64_t)pds.pds[i].base, - (uint64_t)pds.pds[i].size, flags); + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); if (cxl_mode == CXL_SPM) LOG_RESOURCE("specific_purpose_memory", dev, res); else -- To view, visit https://review.coreboot.org/c/coreboot/+/74296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Gerrit-Change-Number: 74296 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi/acpi.c: Follow spec more closely for MADT
by Lean Sheng Tan (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Benjamin Doron, Paul Menzel, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69225 ) Change subject: acpi/acpi.c: Follow spec more closely for MADT ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f Gerrit-Change-Number: 69225 Gerrit-PatchSet: 27 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:55:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek: Add assert for regulator VRF12
by Ruihai Zhou (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74394 ) Change subject: soc/mediatek: Add assert for regulator VRF12 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74394/comment/59e9687a_76abcedd PS1, Line 9: marco typo? -- To view, visit https://review.coreboot.org/c/coreboot/+/74394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Gerrit-Change-Number: 74394 Gerrit-PatchSet: 1 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:41:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu,soc/intel: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 13 Apr '23

13 Apr '23

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74399 ) Change subject: cpu,soc/intel: Separate single SSDT CPU entry ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74399/comment/f2ede8e2_71d60ef8 PS1, Line 422: generate_cpu_entry(device, cpu_id, core_id, num_virt); This loop order determines UUIDs for each CPU Device(). Now, as long as we create a symmetrical entry for each CPU, the order does not really matter. But the UUIDs need/should sync with MADT LAPIC entries? Is it really okay that we use the BSP CPU to create also the AP CPU's entries on some platforms? -- To view, visit https://review.coreboot.org/c/coreboot/+/74399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Gerrit-Change-Number: 74399 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:39:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: vc/intel/fsp: Update JSL FSP headers from v2385.04 to v4155.00
by build bot (Jenkins) (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Saurabh Mishra, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69107 ) Change subject: vc/intel/fsp: Update JSL FSP headers from v2385.04 to v4155.00 ...................................................................... Patch Set 8: Verified-1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174099): https://review.coreboot.org/c/coreboot/+/69107/comment/e2c42ced_3877b3e9 PS8, Line 9: The headers added are generated as per FSP v4155.00. Previous headers were Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4fae89d8d7fbbcb0448222d39dd829bc3f99644 Gerrit-Change-Number: 69107 Gerrit-PatchSet: 8 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:36:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Daniel Rosa Franzini, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 6 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:34:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek: Add assert for regulator VRF12
by Ruihai Zhou (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Hung-Te Lin, cong yang, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74394 ) Change subject: soc/mediatek: Add assert for regulator VRF12 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Gerrit-Change-Number: 74394 Gerrit-PatchSet: 1 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:33:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi/acpi.c: Follow spec more closely for MADT
by Kyösti Mälkki (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Benjamin Doron, Paul Menzel, Arthur Heymans, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69225 ) Change subject: acpi/acpi.c: Follow spec more closely for MADT ...................................................................... Patch Set 27: Code-Review+2 (1 comment) Patchset: PS22: > Yeah, I think these works should somehow merge together to one solution. […] CB:74399 for discussion -- To view, visit https://review.coreboot.org/c/coreboot/+/69225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f Gerrit-Change-Number: 69225 Gerrit-PatchSet: 27 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 07:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2023