coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: mb/google/rex: Initial setup for ramstage/early/romstage gpio config ...
by Kun Liu (Code Review) 17 Apr '23

17 Apr '23

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74475 ) Change subject: mb/google/rex: Initial setup for ramstage/early/romstage gpio config for screebo ...................................................................... mb/google/rex: Initial setup for ramstage/early/romstage gpio config for screebo This adds the initial gpio configuration for the screebo initial variant. BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: liukun11 <liukun11(a)huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 --- M src/mainboard/google/rex/variants/screebo/gpio.c 1 file changed, 422 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74475/1 diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c index b6e346f..83150be 100644 --- a/src/mainboard/google/rex/variants/screebo/gpio.c +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -6,25 +6,426 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 : [] ==> EN_UCAM_PWR */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */ + PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG), + /* GPP_A14 : net NC is not present in the given design */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 : net NC is not present in the given design */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */ + /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), + + /* GPP_A18 : net NC. Test pad. */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), + /* GPP_A21 : [] ==> PMCALERT */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + + /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_B01 : [] ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_B01, 1, DEEP), + /* GPP_B02 : net NC is not present in the given design */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03 : net NC is not present in the given design */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05 : [] ==> SPKR_INT_L_R */ + /* GPP_B05 : net NC is not present in the given design */ + PAD_NC(GPP_B05, NONE), + /* GPP_B06 : [] ==> HP_INT_L_R */ + PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), + /* GPP_B07 : [] ==> EN_SPKR */ + PAD_CFG_GPO(GPP_B07, 1, DEEP), + /* GPP_B08 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_B08, 1, LOCK_CONFIG), + /* GPP_B09 : net NC is not present in the given design */ + PAD_NC(GPP_B09, NONE), + /* GPP_B10 : net NC is not present in the given design */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11 : [] ==> USB_C1_OC_ODL*/ + PAD_CFG_NF_LOCK(GPP_B11, NONE, NF1, LOCK_CONFIG), + /* GPP_B12 : [] ==> SLP_SO_R_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 : [] ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15 : [] ==> USB_OC3# */ + PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* GPP_B17 : net NC. Test pad. */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), + /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ + PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), + /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ + PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), + /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 : net NC. Test pad. */ + PAD_NC(GPP_B23, NONE), + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 0, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), + /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03 : [] ==> SOC_TCP_SMBUS_CLK*/ + PAD_CFG_NF_LOCK(GPP_C03, NONE, NF1, LOCK_CONFIG), + /* GPP_C04 : [] ==> SOC_TCP_SMBUS_SDA*/ + PAD_CFG_NF_LOCK(GPP_C04, NONE, NF1, LOCK_CONFIG), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_C06, 1, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), + /* GPP_C08 : [] ==> SOCHOT_ODL */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), + /* GPP_C09 : net NC is not present in the given design */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10 : net NC is not present in the given design */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 : [] ==> SD_CLKREQ_ODL */ + /* PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),*/ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ + /* PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),*/ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 : [] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* GPP_C16 : [] ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF6), + /* GPP_C17 : [] ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF6), + /* GPP_C18 : [] ==> USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19 : [] ==> USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20 : [] ==> SOC_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_C20, 0, LOCK_CONFIG), + /* GPP_C21 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_C21, 1, LOCK_CONFIG), + /* GPP_C22 : [] ==> USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* GPP_C23 : [] ==> USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + + /* GPP_D00 : net NC is not present in the given design */ + PAD_NC(GPP_D00, NONE), + /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), + /* GPP_D04 : net NC is not present in the given design */ + PAD_NC(GPP_D04, NONE), + /* GPP_D05 : [] ==> UART0_RXD. */ + PAD_CFG_NF_LOCK(GPP_D05, NONE, NF1, LOCK_CONFIG), + /* GPP_D06 : [] ==> UART0_TXD. */ + PAD_CFG_NF_LOCK(GPP_D06, NONE, NF1, LOCK_CONFIG), + /* GPP_D07 : net NC. Test pad. */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08 : net NC. Test pad. */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09 : [] ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), + /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ + /* GPP_D13 : net NC is not present in the given design */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), + /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* GPP_D18 : net NC is not present in the given design */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 : [] ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D20 : net NC is not present in the given design */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21 : net NC is not present in the given design */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22 : net NC. Test pad. */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 : net NC. Test pad. */ + PAD_NC(GPP_D23, NONE), + + /* GPP_E00 : net NC is not present in the given design */ + PAD_NC(GPP_E00, NONE), + /* GPP_E01 : MEM_STRAP_2 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), + /* GPP_E02 : MEM_STRAP_1 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E04 : net NC is not present in the given design */ + PAD_NC(GPP_E04, NONE), + /* GPP_E05 : net NC is not present in the given design */ + PAD_NC(GPP_E05, NONE), + /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : net NC is not present in the given design */ + PAD_NC(GPP_E07, NONE), + /* GPP_E08 : net NC is not present in the given design */ + PAD_NC(GPP_E08, NONE), + /* GPP_E09 : No heuristic was found useful */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), + /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E10, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E11 : [] ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* GPP_E12 : [] ==> MEM_STRAP_3 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 : net NC is not present in the given design */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16 : net NC. Test pad. */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17 : net NC. Test pad. */ + PAD_NC(GPP_E17, NONE), + /* GPP_E22 : [] ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + + /* GPP_F00 : [] ==> CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 : [] ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 : [] ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 : [] ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 : [] ==> CNV_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 : net NC is not present in the given design */ + PAD_NC(GPP_F06, NONE), + /* GPP_F07 : [] ==> UCAM_MCLK_R */ + PAD_CFG_NF(GPP_F07, NONE, DEEP, NF1), + /* GPP_F08 : net NC is not present in the given design */ + PAD_NC(GPP_F08, NONE), + /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */ + /* GPP_F09 : net NC is not present in the given design */ + PAD_NC(GPP_F09, NONE), + /* GPP_F10 : net NC is not present in the given design */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11 : GSP1_SOC_CLK_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5), + /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), + /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), + /* GPP_F14 : net NC. Test pad. */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 : net NC. Test pad. */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 : net NC. Test pad. */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), + /* GPP_F18 : net NC is not present in the given design */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 : [] ==> GPP_F19_STRAP */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 : [] ==> GPP_F20_STRAP */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 : [] ==> GPP_F21_STRAP */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 : net NC is not present in the given design */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 : net NC is not present in the given design */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H04 : net NC is not present in the given design */ + PAD_NC(GPP_H04, NONE), + /* GPP_H05 : net NC is not present in the given design */ + PAD_NC(GPP_H05, NONE), + /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ + PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), + /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ + PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + /* GPP_H11 : net NC is not present in the given design */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13 : [] ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : [] ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ + /* GPP_H15 : net NC is not present in the given design */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00 : net NC is not present in the given design */ + PAD_NC(GPP_S00, NONE), + /* GPP_S01 : net NC is not present in the given design */ + PAD_NC(GPP_S01, NONE), + /* GPP_S02 : net NC is not present in the given design */ + PAD_NC(GPP_S02, NONE), + /* GPP_S03 : net NC is not present in the given design */ + PAD_NC(GPP_S03, NONE), + /* GPP_S04 : net NC is not present in the given design */ + PAD_NC(GPP_S04, NONE), + /* GPP_S05 : net NC is not present in the given design */ + PAD_NC(GPP_S05, NONE), + /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* GPP_V00 : [] ==> BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01 : [] ==> ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04 : [] ==> SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 : [] ==> SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 : [] ==> SOC_SLP_A_L */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V08 : [] ==> SOC_SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 : [] ==> SLP_S5_L */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/ + PAD_NC(GPP_V11, NONE), + /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V14 : [] ==> SOC_WAKE_L */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V22 : [] ==> WCAM_RST_L */ + /* GPP_V22 : net NC is not present in the given design */ + PAD_NC(GPP_V22, NONE), + /* GPP_V23 : [] ==> UCAM_RST_L */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D03, 1, DEEP), + + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + /* A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C21, 0, DEEP), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), +}; + const struct pad_config *variant_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(gpio_table); + return gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Gerrit-Change-Number: 74475 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()
by build bot (Jenkins) (Code Review) 17 Apr '23

17 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74441 ) Change subject: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... Patch Set 2: (1 comment) File src/cpu/intel/speedstep/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174273): https://review.coreboot.org/c/coreboot/+/74441/comment/f786f71f_5c247fd3 PS2, Line 108: #if 0 Consider removing the code enclosed by this #if 0 and its #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Apr 2023 11:49:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ACPI: Add acpigen_write_PTC()
by Kyösti Mälkki (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74473 ) Change subject: ACPI: Add acpigen_write_PTC() ...................................................................... ACPI: Add acpigen_write_PTC() Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 31 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74473/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index d308930..d613bec 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -711,7 +711,7 @@ acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } -void acpigen_write_empty_PTC(void) +void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt) { /* Name (_PTC, Package (0x02) @@ -719,31 +719,35 @@ ResourceTemplate () { Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address + 0x00, // Duty Width + 0x00, // Duty Offset + 0x0000000000000000, // P_CNT IO Address ,) }, ResourceTemplate () { Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address + 0x00, // Duty Width + 0x00, // Duty Offset + 0x0000000000000000, // P_CNT IO Address ,) } }) */ acpi_addr_t addr = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 0, - .bit_offset = 0, + .bit_width = duty_width, + .bit_offset = duty_offset, .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0, + .addrl = p_cnt, .addrh = 0, }; + if (addr.addrl != 0) + addr.space_id = ACPI_ADDRESS_SPACE_IO; + else + addr.space_id = ACPI_ADDRESS_SPACE_FIXED; + acpigen_write_name("_PTC"); acpigen_write_package(2); @@ -756,6 +760,11 @@ acpigen_pop_len(); } +void acpigen_write_empty_PTC(void) +{ + acpigen_write_PTC(0, 0, 0); +} + static void __acpigen_write_method(const char *name, uint8_t flags) { acpigen_emit_byte(METHOD_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index ae50143..180e937 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -431,6 +431,7 @@ void acpigen_write_PPC_NVS(void); void acpigen_write_empty_PCT(void); void acpigen_write_empty_PTC(void); +void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt); void acpigen_write_PRW(u32 wake, u32 level); void acpigen_write_STA(uint8_t status); void acpigen_write_STA_ext(const char *namestring); -- To view, visit https://review.coreboot.org/c/coreboot/+/74473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Gerrit-Change-Number: 74473 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()
by Kyösti Mälkki (Code Review) 17 Apr '23

17 Apr '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74441 to look at the new patch set (#2). Change subject: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/include/cpu/intel/speedstep.h M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/lpc.c 8 files changed, 56 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74441/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device()
by Kyösti Mälkki (Code Review) 17 Apr '23

17 Apr '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74440 to look at the new patch set (#2). Change subject: asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() ...................................................................... asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() FADT duty_width/duty_offset fields, together with P_CNT (previously P_BLK) IO address are provided with _PTC entry. FADT p_lvl2/3_lat fields had values that disabled C2/C3 state transitions so _CST entries are not required. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/fadt.c 2 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74440/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Gerrit-Change-Number: 74440 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/speedstep: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74400 to look at the new patch set (#4). Change subject: cpu/intel/speedstep: Separate single SSDT CPU entry ...................................................................... cpu/intel/speedstep: Separate single SSDT CPU entry Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/southbridge/intel/i82371eb/acpi_tables.c 2 files changed, 67 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74400/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Gerrit-Change-Number: 74400 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static
by Sridhar Siricilla (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Tarun Tuli, SRIDHAR SIRICILLA, Subrata Banik, Kapil Porwal, Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74388 ) Change subject: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74388/comment/7a2de9ec_371929db PS6, Line 1219: vboot_recovery_mode_enabled > > This seems to be redundant considering the execution path starting from store_ish_version() […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Gerrit-Change-Number: 74388 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Mon, 17 Apr 2023 11:37:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in gerrit-avatars[master]: Add Gerrit avatar for 1004568
by James R T (Code Review) 17 Apr '23

17 Apr '23

James R T has submitted this change. ( https://review.coreboot.org/c/gerrit-avatars/+/74495 ) Change subject: Add Gerrit avatar for 1004568 ...................................................................... Add Gerrit avatar for 1004568 Signed-off-by: James Raphael Tiovalen <jamestiotio(a)gmail.com> Change-Id: If6162054c6a7e420a1fd5483306d8993e0056ee4 --- A 1004568.jpg 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified; Looks good to me, approved diff --git a/1004568.jpg b/1004568.jpg new file mode 100644 index 0000000..924839d --- /dev/null +++ b/1004568.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/74495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If6162054c6a7e420a1fd5483306d8993e0056ee4 Gerrit-Change-Number: 74495 Gerrit-PatchSet: 1 Gerrit-Owner: James R T <jamestiotio(a)gmail.com> Gerrit-Reviewer: James R T <jamestiotio(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in gerrit-avatars[master]: Add Gerrit avatar for 1004568
by James R T (Code Review) 17 Apr '23

17 Apr '23

James R T has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/74495 ) Change subject: Add Gerrit avatar for 1004568 ...................................................................... Add Gerrit avatar for 1004568 Signed-off-by: James Raphael Tiovalen <jamestiotio(a)gmail.com> Change-Id: If6162054c6a7e420a1fd5483306d8993e0056ee4 --- A 1004568.jpg 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/95/74495/1 diff --git a/1004568.jpg b/1004568.jpg new file mode 100644 index 0000000..924839d --- /dev/null +++ b/1004568.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/74495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If6162054c6a7e420a1fd5483306d8993e0056ee4 Gerrit-Change-Number: 74495 Gerrit-PatchSet: 1 Gerrit-Owner: James R T <jamestiotio(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state
by Sean Rhodes (Code Review) 17 Apr '23

17 Apr '23

Attention is currently required from: Nico Huber, Sean Rhodes. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74406 ) Change subject: soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d Gerrit-Change-Number: 74406 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 17 Apr 2023 10:28:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023